CPU Verification Engineer (RISC-V)

Qualcomm

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $167,100–$250,700 / yr
Posted: 39 days ago
Closes: Nov 3, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $209k

$140k most similar roles pay here $263k

This role pays more than 70% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · CPU Verification Engineer (RISC-V)

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As a Design Verification Engineer at Qualcomm Technologies, Inc., you will join the CPU and SOC Architecture team to validate micro-architectures by developing detailed test plans and coverage strategies based on high-level system requirements. Your daily tasks include creating verification methodologies and environments, executing verification plans, and tracking progress through various metrics. You will need extensive knowledge of RISC-V instruction sets and expertise in areas like cache coherence, memory ordering, and prefetching. Proficiency with verification tools such as simulators, coverage collection systems, and waveform viewers is essential, along with experience in writing testbenches and assembly code. This role involves working on complex micro-processor functions at both block/unit and subsystem/chip levels to ensure designs are launch-ready for high-scale products.

Skills

RISC-V Cache Coherence Memory ordering and Consistency Prefetching Branch Prediction Rename Speculative execution Address Translation Memory Management Random Instruction Sequencing Testbenches Transactors Assembly code Verification Methodologies Simulators Coverage collection Gate-level Simulation Waveform viewers Mixed signal Verification

What you'll do

Develop detailed test and coverage plans based on architecture and micro-architecture.
Create verification methodology ensuring scalability across different environments.
Design verification environment including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans to ensure design bring-up and regression testing.
Track and report progress using various metrics for DV tasks.

What we're looking for

Extensive knowledge of RISC-V Instruction Set Architecture.
Deep understanding of CPU verification functions and architectures.
Experience in developing detailed test and coverage plans.
Proficiency in creating scalable verification environments and methodologies.
Ability to execute verification plans and debug test failures independently.
BS degree in Computer Engineering, Electrical Engineering, or Computer Science.
Knowledge of random instruction sequencing and testing at various levels.

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