SoC Physical Design Engineer, STA/Timing

What you'll do

• Execute the physical implementation of design partitions from netlist to tapeout for complex SoCs.
• Analyze timing paths deeply to identify and resolve critical timing issues.
• Develop and implement timing ECOs to ensure successful project tapeouts.
• Create and maintain scripts and methodologies for analysis and automated runs using TCL, Perl, or Python.
• Build and maintain the underlying timing infrastructure for the design process.
• Collaborate with design teams to debug constraints and facilitate logic changes to improve timing.
• Develop technical documentation, guidelines, and specifications for the physical design team.

What we're looking for

• Minimum BS degree and 10+ years of relevant industry experience.
• Strong programming skills with TCL.
• Experience with large design STA and/or Timing Closure (preferred).
• Experience with timing of large high-performance SoC designs in sub-micron technologies (preferred).
• Deep understanding of noise, crosstalk, OCV, and other timing modeling effects (preferred).
• Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation (preferred).
• Experience in ECO techniques and implementation (preferred).
• Experience with other scripting languages such as Perl or Python (preferred).