SoC Physical Design Engineer, STA/Timing

Apple Inc

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Work type: On-site
Location: Beaverton, OR
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

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TL;DR · SoC Physical Design Engineer, STA/Timing

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As an SoC Physical Design Engineer, STA/Timing, you will join the Physical Design team to manage the physical implementation of design partitions from netlist to tapeout for highly complex SoCs using state of the art process technology. Your daily responsibilities include performing deep analysis of timing paths to identify key issues, creating timing ECOs for project tapeouts, and implementing timing infrastructure. You will collaborate with design teams to debug constraints, facilitate logic changes to improve timing, and create documentation or guidelines. Required technical skills include experience with STA, noise, crosstalk, and OCV effects. Preferred qualifications include proficiency in Perl and TCL, circuit modeling with SPICE models, and experience with timing closure methodologies for large high-performance SoC designs in sub-micron technologies.

Skills

STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout

What you'll do

Execute physical implementation of design partitions from netlist to tapeout.
Perform deep analysis of timing paths to identify and resolve key issues.
Create and implement timing ECOs for project tapeouts.
Develop and maintain scripts and methodologies for analysis and design runs.
Implement timing infrastructure for complex SoC designs.
Debug design constraints and facilitate logic changes to improve timing.
Create technical documentation, guidelines, and specifications for the design process.

What we're looking for

Minimum Bachelor's degree.
Experience with STA.
Experience with noise, crosstalk, and/or OCV effects.
Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Experience with STA and methodologies for timing closure (preferred).
Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Good programming skills with Perl and TCL (preferred).
Experience with large design STA and Timing Closure (preferred).