SOC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $177k

$117k $242k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $168,500–$230,087 — the blue band above. At the midpoint, this role pays about $177k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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The SOC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification at the block, subsystem, and top-level SOC levels. You will own a verification scope from initial test planning through coverage closure and signoff, building reusable testbenches and verification environments using metric-driven methodologies. Key responsibilities include writing directed and constrained-random tests, debugging failures, and verifying low-power design intent using UPF. You will work on components like the Power Management Unit, CPU subsystem, DMA, PCIe, and bus fabric, while verifying end-to-end WiFi and Bluetooth traffic flows. Required skills include SystemVerilog, Verilog, and UVM. You will also explore AI-assisted verification techniques and apply formal verification tools like JasperGold to solve complex wireless silicon integration problems.

Skills

SystemVerilog Verilog UVM UPF Python C++ Perl Formal Verification JasperGold ASIC SOC PCIe AXI AHB SVA WiFi Bluetooth

What you'll do

Develop reusable UVM testbenches for block, subsystem, and top-level SOC verification.
Create directed and constrained-random tests to drive coverage closure and signoff.
Debug hardware failures and corner cases while managing the bug tracking process.
Verify low-power design intent using UPF within assigned IP or subsystem scopes.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to SOC integration.
Build and improve automated regression flows and verification methodologies.
Apply AI-assisted verification techniques to improve test generation and debug productivity.
Support post-silicon bring-up activities as needed.

What we're looking for

Minimum requirement of a bachelor's degree.
Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols (preferred).

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