SI/PI Tech Project Manager

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, CO
Employment
Full-time
Posted
49 days ago
Freshness
Confirmed live yesterday
Closes
Feb 13, 2027

Market check

Salary context

How this pay compares to similar roles

Similar $184k
$135k $235k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $154,975–$213,656.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · SI/PI Tech Project Manager

The SI/PI Tech Project Manager joins a worldwide R&D team to lead engineers in designing complex flip-chip-BGA packages, PCBs, and system channel links for high-performance ASICs. This role involves managing project plans for over twenty concurrent designs, tracking scope, schedules, and resources while developing technical methodologies for signal and power integrity solutions. You will oversee team productivity, communicate risks, and collaborate with vendors and cross-functional partners. Key technical responsibilities include SI/PI EDA extractions, simulations, lab measurements, and correlation efforts for SerDes at 448G and higher, Optics, 5G RF/Microwave ADC/DAC, HBM, and DDR5. The work addresses high-speed SerDes and very-high-power-delivery needs within the domains of artificial intelligence, networking, high-performance computing, and 5G base stations.

What you'll do

  • Track project plans for over 20 concurrent package and PCB designs regarding scope, schedules, and resources.
  • Create technical methodologies for signal and power integrity solutions.
  • Manage and develop the engineering team by identifying individual skill sets to maximize productivity.
  • Communicate project plans, status updates, next steps, and risks clearly to customers and stakeholders.
  • Oversee SI/PI EDA extractions, simulations, and lab measurement correlation efforts.
  • Manage lab equipment needs and the package and PCB lifecycle design flows.
  • Develop automation code to support design data and project workflows.

What we're looking for

  • BSEE degree (preferred).
  • 12+ years of experience in ASIC and system signal and power integrity for high-speed SerDes (preferred).
  • Minimum of 3 years of experience in management (preferred).
  • Previous experience managing people and projects (preferred).
  • Knowledge of package-level, PCB-level, and/or system level signal integrity and power integrity.
  • Technical understanding of SI/PI EDA extractions, simulations, SerDes channel results, and lab measurements.
  • Experience with package and PCB lifecycle, design flows, and automation code development.
  • Strong self-management, organization, and clear communication skills.

More like this

Similar roles

ASIC Package Design Manager

Broadcom

Fort Collins, CO 97 days ago
Flip-chip-BGA ASIC SerDes HBM DDR5 Signal Integrity Power Integrity Layout DFx Thermal Modeling Automation Project Management Simulation RF Microwave
10+ yrs exp

ASIC Package Design Project Manager

Broadcom

Fort Collins, CO 5 days ago $129,400–$207,000
Package Design ASIC SerDes HBM DDR5 Signal Integrity Power Integrity DFx Thermal Modeling Automation Project Management Layout Simulations RF Microwave ADC DAC
10+ yrs exp

Package Design Engineer

Broadcom

San Jose, CA +2 148 days ago
IC Package Design Flip-chip BGA SerDes Signal Integrity Power Integrity ASIC HBM DDR5 RF Microwave Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout Automation Manufacturability
10+ yrs exp

ASIC Package Design Engineer

Broadcom

San Jose, CA +2 8 days ago $143,800–$230,000
IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC
10+ yrs exp

Package Design Engineer

Broadcom

San Jose, CA +2 26 days ago $101,000–$162,000
IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity Thermal Manufacturability Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout HBM DDR5 RF Microwave ADC DAC
5+ yrs exp

Package Design Engineer

Broadcom

San Jose, CA +2 49 days ago $82,500–$132,000
Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout HBM DDR5 RF Microwave ADC DAC Manufacturability Automation
2+ yrs exp