Signoff Static Timing Analysis and Spice CAD Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
79 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 21, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k
This role $175k
$129k most similar roles pay here $241k

This role pays less than 71% of similar roles. Most pay $172,375–$216,250 — the shaded band above. At the midpoint, this role pays about $175k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Signoff Static Timing Analysis and Spice CAD Engineer

As a Signoff Static Timing Analysis and Spice CAD Engineer on the Global CAD team, you will develop tools and methodologies to improve accuracy and reduce turnaround time for Snapdragon chips. You will be responsible for improving timing and cell characterization methods across various mobile, compute, AI, and IoT platforms. Your daily work involves performing spice correlation, validating STA tools version-to-version, managing ticket queues for design teams, and interfacing with EDA vendors to ensure production-ready toolsets. You will also collaborate with the AI team on research initiatives involving genAI/ML and develop good-by-construction hierarchical solutions. The role requires expertise in STA features, timing concepts, and spice simulation. Necessary technical skills include proficiency in Python and TCL scripting to support complex design flows across advanced foundry process nodes for subsystems like GPU, CPU, and Modem.

What you'll do

  • Improve timing and cell characterization methodologies for diverse mobile, compute, and AI chips.
  • Validate new cell characterization features through spice correlation and CAD development.
  • Correlate STA tools with spice results and perform version-to-version validation.
  • Resolve technical requests from Snapdragon design teams via established ticket queues.
  • Interface with EDA vendors to ensure production-ready toolsets meet project requirements.
  • Set up, augment, and maintain regressions for complex STA designs.
  • Research and develop AI/ML initiatives to reduce compute time and improve turnaround.
  • Serve as a domain expert to deep dive into and resolve complex STA or spice issues.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Master's degree in Science, Engineering, or a related field.
  • PhD in Science, Engineering, or a related field.
  • 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level.
  • 2-6 years of experience with scripting tools and programming languages, preferably Python and TCL.
  • 4+ years of experience in ASIC design, verification, validation, integration, or related work for Bachelor's degree holders.
  • 3+ years of experience in ASIC design, verification, validation, integration, or related work for Master's degree holders.
  • 2+ years of experience in ASIC design, verification, validation, integration, or related work for PhD holders.

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