SOC Verification and Methodology Engineer

Qualcomm

Actively hiring
San Diego, CA Posted 26 days ago $98,500–$147,700 / year
View original post Log in to save

At a glance

AI generated

TL;DR

Join Qualcomm Technologies as an ASIC Design Verification Engineer within their Global SOC organization, a team of top-tier engineers driving the development of cutting-edge 5G products from low-power Snapdragon chips to AI/ML and autonomous driving solutions. Your role involves developing comprehensive verification methodologies, creating detailed test plans, and executing tests to ensure high-quality SoC designs. You will collaborate with architects, designers, and other teams globally to innovate new verification techniques and tools, adhering to industry standards while pushing the boundaries of what is possible in system-level integration validation. Essential skills include SystemVerilog/UVM expertise, assertion-based verification methodology, and experience handling full verification cycles from planning to tapeout for large-scale hardware designs. Preferred qualifications enhance your candidacy with knowledge in SOC architecture, ARM SBSA, heterogenous multi-die systems, and scripting languages like Perl or Python.

Skills

SystemVerilog UVM Assertions Coverage-based Verification Test Planning Tapeout Perl Python Formal Verification ARM Architecture SOC Architecture DSP AMBA Bus DDR GPU Multimedia SBSA Heterogeneous Multi-die System D2D Interfaces Pre-silicon Emulation

What you'll do

  • Develop detailed verification plans and test strategies for complex SOC designs.
  • Execute comprehensive verification tests using System Verilog and UVM methodologies.
  • Identify and resolve intricate design issues through debugging and analysis.
  • Innovate new verification solutions and methodologies to enhance efficiency.
  • Maintain high-quality standards in verification processes and documentation.

What we're looking for

  • Minimum 2+ years of design verification experience.
  • Strong understanding of SystemVerilog/UVM and assertion-based verification methodology.
  • Experience in full-cycle verification from test planning to tapeout for large-scale hardware designs.
  • Bachelor’s degree in Science, Engineering, or related field.
  • Ability to collaborate effectively with cross-functional teams globally.
  • Knowledge of SOC architecture and experience with CPU (preferably ARM) design.

Market check

Salary context

This $98,500–$147,700 range sits above 8% of similar postings on FindRole.

Peer median band

$142,200–$220,950

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$153,100–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $148,300–$224,400 across 531 roles with salary data.

Most-posted roles

View all roles at Qualcomm

More like this

Similar roles

SOC Verification and Methodology Engineer

Qualcomm

San Diego, Ca,Us, US 52 days ago $115,600–$173,400
SystemVerilog UVM Assertions Coverage-Based_Verification Test_Planning Tapeout SOC_Architecture ARM_Knowledge DSP AMBA_Bus DDR GPU Multimedia SBSA UCIe CXL Pre-Silicon_Emulation Power_Design Perl Python Formal_Verification

SOC Systems Performance Engineer

Qualcomm

San Diego, Ca,Us, US 32 days ago $99,400–$149,200
C C++ SystemC Linux ARM Python VLSI Docker Git Jenkins CI/CD AWS Google Cloud Platform Azure Terraform Kubernetes PostgreSQL MongoDB Prometheus Grafana

SoC Power Validation Engineer

Qualcomm

San Diego, Ca,Us, US 48 days ago $115,600–$173,400
Python C JTAG Lauterbach Trace32 RTL Vmin/Fmax measurements Silicon parametric testing Logic analyzers Oscilloscopes Power validation Thermal analysis Performance characterization Regression testing PVT testing Validation automation Post-silicon validation

Senior SoC Verification Methodology Engineer

Nvidia

Us, Ca, Santa Clara, US 132 days ago $168,000–$264,500
SystemVerilog UVM Python Perl RTL simulation Hardware emulation FPGA prototyping C-model verification Verification IP Reusable verification components EDA tools CI/CD