Senior STA Signoff Methodology Engineer

What you'll do

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows addressing aging, self-heating, thermal effects, IR drop, and electromigration.
• Create tools and methodologies to improve design performance and reliability beyond standard EDA tool capabilities.
• Define and deploy sophisticated timing-signoff strategies for high-performance silicon across multiple product lines.
• Perform extensive data analysis using Python or JMP to improve STA-to-silicon correlation.
• Work across STA, constraints, and timing and power optimization to ensure robust chip performance.

What we're looking for

• MS in Electrical or Computer Engineering, or equivalent experience.
• 8 years of experience in ASIC design and timing.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proficiency in low-power techniques including multi-Vt design, clock gating, power gating, and DVFS.
• Understanding of signal/power integrity, crosstalk, electromigration, noise, OCV, timing margins, and IR drop.
• Experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
• Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Familiarity with 3D IC integration, die stacking, and packaging (preferred); Proficiency in Tcl and Python (preferred).