Senior STA Signoff Methodology Engineer

What you'll do

• Run large-scale SPICE simulations and STA experiments to model advanced technology impacts on chip timing.
• Develop STA and PNR flows addressing aging, self-heating, thermal effects, IR drop, and electromigration.
• Define and deploy sophisticated timing-signoff strategies for high-performance silicon.
• Develop custom tools and methodologies to improve design performance and reliability beyond standard EDA capabilities.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python or JMP to improve STA-to-silicon correlation.

What we're looking for

• MS in Electrical or Computer Engineering, or equivalent experience.
• 8 years of experience in ASIC design and timing.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
• Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
• Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Strong communication skills and a collaborative working style.
• Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure (preferred).
• Strong data-analysis and modeling skills employing Python, JMP, or similar platforms (preferred).
• Proficiency in Tcl and Python; C++ experience is a plus (preferred).