Senior Circuit Methodology Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 168 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $216k

$129k $279k

below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $159,362–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Circuit Methodology Engineer

Role Posting Log in to save

The Senior Circuit Methodology Engineer will join the circuit design engineering team to provide infrastructure support for circuit design and methodology. This role involves owning and evolving compute and GPU infrastructure in coordination with Farm, IT, CAD, and GPU infrastructure teams to ensure the stability of mixed-signal design and verification flows. Key responsibilities include designing, developing, and maintaining flows on large-scale compute farms, monitoring farm health, identifying bottlenecks, and implementing solutions to improve throughput and utilization. The engineer will evaluate new resources, build automation tools for job submission and reporting, and provide user support by debugging complex multi-layer issues. Required skills include Python, Perl, and experience with Cadence/Synopsys systems like Virtuoso and Custom Compiler, as well as LSF and Slurm job schedulers.

Skills

Python Perl LSF Slurm Cadence Synopsys Virtuoso Custom Compiler EDA Circuit Design GPU Infrastructure Job Schedulers Automation mixed‑signal design Verification Flows

What you'll do

Design, develop, and maintain circuit design and verification flows for large-scale compute and GPU farms.
Monitor farm health and job behavior to identify bottlenecks and improve throughput and utilization.
Bring up and release new compute and GPU infrastructure for the circuit design team.
Evaluate and qualify new compute resources, schedulers, and EDA infrastructure components.
Build automation and tooling for flow setup, job submission, resource allocation, and reporting.
Track performance metrics like queue times and failure rates to lead farm efficiency improvement projects.
Debug flow, infrastructure, and job-scheduling issues to implement permanent fixes for users.
Develop documentation, training materials, and best-practice guidelines for the circuit design compute environment.

What we're looking for

BSEE, BSCE, or equivalent experience.
Mid-level programming skill in Python and Perl is a must.
8 plus years of working experience related to circuit design methodology using Cadence/Synopsys based systems.
Experience with job schedulers and compute farms, primarily LSF and Slurm.
Proven ability to debug complex multi-layer issues spanning flows, scripts, tools, and infrastructure.
Strong communication skills and ability to partner with diverse engineering teams.
Previous design experience (preferred).
Exposure to circuit design workloads (preferred).

Save