Senior Circuit Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
122 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $216k
$129k most similar roles pay here $279k

This role pays more than 83% of similar roles. Most pay $168,725–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Circuit Methodology Engineer

As a Senior Circuit Methodology Engineer, you will join the circuit design engineering team to provide critical infrastructure support for mixed-signal design and verification flows. You will own and evolve compute and GPU infrastructure by collaborating with Farm, IT, CAD, and GPU infrastructure teams. Your daily responsibilities include designing, developing, and maintaining flow systems on large-scale farms across multiple geographies using various job schedulers. You will monitor farm health, identify bottlenecks, qualify new resources, and build automation tools for job submission and resource allocation. The role requires proficiency in Python, Perl, and experience with Cadence or Synopsys based systems like Virtuoso and Custom Compiler. Additionally, you must navigate LSF and Slurm schedulers to manage infrastructure while providing technical support and developing documentation to ensure efficient circuit design operations across the entire department.

What you'll do

  • Design, develop, and maintain circuit design and verification flows on large-scale compute and GPU farms.
  • Monitor farm health and job behavior to identify bottlenecks and improve throughput and utilization.
  • Bring up and release new compute and GPU infrastructure for the circuit design team.
  • Evaluate and qualify new compute resources, schedulers, and related EDA infrastructure components.
  • Build automation and tooling to streamline flow setup, job submission, and resource allocation.
  • Track performance metrics like queue times and failure rates to lead farm efficiency projects.
  • Provide user support by debugging complex issues in flows, infrastructure, and job scheduling.
  • Develop documentation, training materials, and best-practice guidelines for the circuit design environment.

What we're looking for

  • Bachelor of Science in Electrical Engineering (BSEE), Computer Engineering (BSCE), or equivalent experience.
  • Mid-level programming skills in Python and Perl are required.
  • Experience related to circuit design methodology using Cadence/Synopsys based systems.
  • Experience with job schedulers and compute farms, specifically LSF and Slurm.
  • Proven ability to debug complex multi-layer issues spanning flows, scripts, tools, and infrastructure.
  • Strong communication skills and the ability to partner with diverse engineering teams.
  • Previous circuit design experience is highly preferred.
  • Exposure to circuit design workloads is beneficial.

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