Senior Specialist, Electrical Engineering - FPGA Verification Engineer

L3Harris

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Work type: On-site
Location: Palm Bay, FL
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $184k

$133k most similar roles pay here $228k

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About L3Harris

L3Harris Technologies is a US aerospace and defense technology company providing space and airborne systems, communications, electronic warfare, and missile propulsion solutions for government and commercial customers.

L3Harris currently has 583 open roles on FindRole.

Listed pay typically runs $106,500–$197,500 across 231 roles with salary data.

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At a glance

TL;DR · Senior Specialist, Electrical Engineering - FPGA Verification Engineer

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Senior Specialist, Electrical Engineering - FPGA Verification Engineer joins the engineering team to develop and execute verification plans for complex digital designs. The role involves building reusable UVM-based testbenches, creating constrained-random and directed tests, and developing agents, monitors, predictors, and scoreboards. The engineer will analyze coverage metrics, debug simulation failures, and ensure functional correctness throughout the development lifecycle while collaborating with design and systems engineers. Key technical requirements include proficiency in SystemVerilog, SystemVerilog Assertions, and scripting languages like Python, Perl, or bash within Linux environments. Candidates should possess experience with Altera or Xilinx architectures, high-speed serial protocols such as PCI Express and Ethernet, and tools like Vivado or Quartus. The work focuses on the FPGA design process, including requirements generation, peer reviews, and ensuring robust designs through rigorous verification of hardware components.

Skills

UVM SystemVerilog FPGA Xilinx Altera Vivado Quartus Python C++ VHDL PCI Express Ethernet SRIO Linux Git SVN Bash Perl DO-254

What you'll do

Develop and execute comprehensive FPGA verification plans to ensure design integrity.
Architect UVM test cases for individual blocks and sub-blocks within an FPGA.
Build reusable UVM components including agents, top-level testbench modules, and environments.
Create constrained-random and directed tests using SystemVerilog to validate complex digital designs.
Define and implement functional coverage models based on DUT requirements to close code coverage.
Develop UVM-based drivers, monitors, predictors, and scoreboards for specific hardware requirements.
Debug simulation failures and identify design issues or corner cases to improve robustness.
Automate regression testing and manage verification environments using scripting languages like Python or Perl.

What we're looking for

Bachelor's degree and 6 years of experience, a graduate degree and 4 years of experience, or 10 years of experience without a degree.
Ability to obtain U.S. government clearance.
Experience developing and executing verification plans and building reusable UVM-based testbenches.
Proficiency in SystemVerilog, assertion-based verification, and Object Oriented Programming concepts (preferred).
Proficiency in scripting languages such as bash/csh, Perl, or Python (preferred).
Experience with Altera or Xilinx/AMD FPGA architectures and Vivado or Quartus tool suites (preferred).
Experience with high-speed serial protocols, network protocols, and SoC designs (preferred).
Security clearance.