This role pays more than
84%
of similar roles. Most pay
$168,500–$216,250
— the shaded band above.
At the midpoint, this role pays about
$222k
versus about
$192k
for comparable roles.
Based on 240 similar postings.
Employer
About Anduril Industries
Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.
Anduril Industries currently has
1747 open roles
on FindRole.
Listed pay typically runs
$146,000–$194,000
across 1544 roles with salary data.
The Senior FPGA Verification Engineer joins the Imaging team to support the development of new product lines involving computer vision, perception, electro-optical, infrared, and sensor data. Working within an interdisciplinary technical team, you will design verification environments using SystemVerilog or OVM/UVM, develop testbenches for RTL blocks using VHDL or SystemVerilog, and create comprehensive test plans with code and functional coverage tracking. You will also provide technical leadership by breaking down work, planning activities, and reporting status while recommending improvements for ASIC and FPGA verification flows. Required skills include experience with constrained-random testing, assertion-based verification, and version control systems like Git or Subversion. Preferred qualifications include proficiency in Unix/Linux environments, scripting languages such as Python or C++, and familiarity with tools like QuestaSim, Synplify, Quartus, or Vivado to solve complex hardware challenges.
Design and architect verification environments using SystemVerilog or OVM/UVM.
Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
Create written test plans, track code coverage, and monitor functional coverage.
Recommend new tools and practices to improve ASIC and FPGA verification flows.
Provide technical leadership by breaking down work, planning activities, and reporting status.
Contribute to engineering estimates for new program pursuits.
Manage source code and configuration integrity using revision control systems like Git.
What we're looking for
A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices.
Experience designing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
Proven ability to design and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
Experience using revision control systems such as Git or Subversion.
Eligible to obtain and maintain an active U.S. Secret security clearance.
Proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard tools like QuestaSim, Synplify, Quartus, or Vivado (preferred).