Senior FPGA Verification Engineer

Anduril Industries

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Boulder, CO
Salary
$165,000–$218,000 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $192k
$135k most similar roles pay here $229k

This role pays more than 60% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $192k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1747 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1544 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer

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The Senior FPGA Verification Engineer joins the Imaging team to support the design of new product lines involving computer vision, perception, electro-optical, infrared, and sensor data. In this role, you will work with an interdisciplinary technical team to define designs, build prototypes for ground and flight testing, and mature those prototypes into final products. Your daily responsibilities include designing verification environments using SystemVerilog or OVM/UVM, creating test plans, tracking code and functional coverage, and developing testbenches for RTL blocks using VHDL or SystemVerilog. You will also provide technical leadership, manage project activities, and recommend improvements for ASIC and FPGA verification flows. Required skills include proficiency in VHDL, Verilog, and Git, while preferred qualifications include experience with Python, C++, Vivado, Quartus, and standard lab validation equipment to solve complex imaging hardware challenges.

Skills

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC Python C++ C Perl Shell Git Subversion QuestaSim Synplify Quartus Vivado Linux Unix

What you'll do

  • Design and architect verification environments using SystemVerilog or OVM/UVM.
  • Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
  • Create written test plans, track code coverage, and monitor functional coverage.
  • Recommend new tools and practices to improve ASIC and FPGA verification flows.
  • Provide technical leadership by breaking down work, planning activities, and reporting status.
  • Contribute to engineering estimates for new program pursuits.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 8+ years of experience developing HDL firmware for FPGA devices.
  • Experience designing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
  • Proven ability to design and execute verification testbenches for RTL blocks using VHDL and SystemVerilog.
  • Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
  • Experience using revision control systems such as Git or Subversion.
  • Eligible to obtain and maintain an active U.S. Secret security clearance.
  • Proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard tools like QuestaSim, Synplify, Quartus, or Vivado (preferred).

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