Senior Software R&D Engineer, ECO Route - VLSI EDA

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Posted: 12 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $216k

$138k most similar roles pay here $278k

This role pays more than 70% of similar roles. Most pay $172,000–$222,000 — the shaded band above. At the midpoint, this role pays about $216k versus about $197k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Software R&D Engineer, ECO Route - VLSI EDA

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As a Senior Software R&D Engineer, ECO Route - VLSI EDA, you will join the team developing highly optimized internal EDA technology to invent next-generation physical design algorithms focused on ECO routing and physical optimization. You will develop incremental physical-design technology for high-performance logic changes with DRC and parasitic awareness while inventing detailed-routing algorithms to solve complex discrete and continuous optimization problems from manufacturing constraints. Your work involves creating cross-domain optimization tools that integrate logic, timing, clocks, testability, power distribution, placement, and routing. You will own the full lifecycle from algorithm invention through implementation, validation, and deployment. The role requires expertise in C++, high-performance software architecture, data structures, and memory efficiency. You must possess a deep understanding of detailed routing, pin access, and DRC-aware implementation to solve problems related to advanced manufacturing processes and high-speed interconnects.

Skills

C++ EDA Physical Design Routing Algorithms Machine Learning SAT Solvers LLMs Reinforcement Learning GNNs Combinatorial Optimization Data Structures Algorithm Development DFT IR Drop Reduction Logic Synthesis Power Distribution Parallel Computing

What you'll do

Develop incremental physical-design technology to implement high-performance logic changes with DRC and parasitic awareness.
Invent detailed-routing algorithms for complex discrete and continuous optimization problems in advanced manufacturing processes.
Create cross-domain optimization tools that simultaneously consider logic, timing, clocks, power distribution, and routing.
Own the full lifecycle of algorithm development from initial invention through implementation, validation, and production deployment.
Develop high-performance C++ software using optimized data structures and memory-efficient architectures.
Implement advanced design rules for pin access, route optimization, and DRC-aware manufacturing constraints.
Optimize physical designs by integrating logic restructuring, technology mapping, and SAT solvers.

What we're looking for

MS, PhD, or equivalent experience.
5+ years of relevant experience.
Strong expertise in C++, high-performance software architecture, and algorithm development.
Deep understanding of detailed routing, including advanced design rules, pin access, route optimization, and DRC-aware implementation.
Understanding of areas impacted by ECOs, such as clock distribution, DFT, and power delivery.
Authorization to work on export controlled data for CPUs, GPUs, LPUs, and communication networks.