Senior Software R&D Engineer, ECO Route, VLSI EDA

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 57 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $216k

$141k $278k

below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $169,050–$222,000 — the blue band above. At the midpoint, this role pays about $216k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Software R&D Engineer, ECO Route, VLSI EDA

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The Senior Software R&D Engineer, ECO Route - VLSI EDA joins the team developing highly optimized internal EDA technology. This role involves inventing the next generation of detailed physical design algorithms, specifically focusing on ECO routing and physical optimization. You will develop incremental physical-design technology to implement high-performance logic changes with DRC and parasitic awareness for all-layer and metal-only ECOs. Responsibilities include crafting cross-domain optimization tools for logic, timing, clocks, testability, power distribution, and placement. You will own problems from algorithm invention through production deployment. Required skills include expertise in C++, high-performance software architecture, data structures, and memory efficiency. You must understand detailed routing, design rules, pin access, and DRC-aware implementation. The work addresses complex discrete and continuous optimization problems within the latest manufacturing processes.

Skills

C++ Algorithm Development Machine Learning LLMs Reinforcement Learning GNNs SAT Solvers EDA ECO Routing Physical Design Logic Synthesis DFT DRC Combinatorial Optimization Data Structures Memory Efficiency

What you'll do

Develop incremental physical-design technology to implement high-performance logic changes with DRC and parasitic awareness.
Invent detailed-routing algorithms to solve discrete and continuous optimization problems from manufacturing DRC constraints.
Craft cross-domain optimization tools that simultaneously consider logic, timing, clocks, testability, power, placement, and routing.
Own the full lifecycle of problems from algorithm invention through implementation, validation, and production deployment.
Implement high-performance C++ software using efficient data structures and memory management.
Optimize ECO routing for applications including timing, power, incremental logic synthesis, and precision clock-tree tuning.

What we're looking for

MS, PhD, or equivalent experience.
5+ years of relevant experience.
Strong expertise in C++, high-performance software architecture, and algorithm development.
Deep understanding of detailed routing, including advanced design rules, pin access, route optimization, and DRC-aware implementation.
Understanding of areas co-optimized with ECOs, including clock distribution, DFT, and power delivery.
Authorization to work on export controlled data arising in CPUs, GPUs, LPUs, and communication networks.
Familiarity with logic and physical co-optimization principles, including logic restructuring, technology mapping, and using SAT solvers (preferred).
Experience with placement, legalization, IR drop reduction, or applying machine learning techniques to physical design (preferred).