Software R&D Engineer, RTL Optimization Tools

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $136,000–$218,500 / yr
Posted: 92 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k

This role $177k

$125k most similar roles pay here $236k

This role pays less than 58% of similar roles. Most pay $160,862–$214,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Software R&D Engineer, RTL Optimization Tools

Role Posting Log in to save

As a Software R&D Engineer, RTL Optimization Tools, you will join a team developing internal EDA tools by fusing parallel computing, machine learning, and novel algorithms in C++. You will invent methods for parallel, graph-based RTL traversal and analysis while devising strategies to evaluate the impact of design changes on data path latency, power, and clocking. Your work involves exploring LLMs, GNNs, GANs, and Reinforcement Learning to automate RTL modifications and developing high-performance algorithms for clustering and logic synthesis. The role requires expertise in C++, Verilog, SystemVerilog, and EDA techniques like static timing analysis and SAT solvers. You will solve complex problems related to large-scale RTL quality, timing, and power optimization while navigating technical domains such as DFT, scan chain insertion, and power gating to improve hardware design productivity for advanced systems.

Skills

C++ RTL Verilog SystemVerilog Machine Learning Reinforcement Learning EDA Logic Synthesis Static Timing Analysis SAT Solvers Multithreading Distributed Computing DFT Power Gating Clock Distribution

What you'll do

Invent new methods for parallel, graph-based RTL traversal, analysis, and manipulation.
Develop strategies to analyze the impact of RTL changes on data path latency, power, and DFT.
Explore LLMs, GNNs, GANs, and Reinforcement Learning to automatically suggest or implement RTL modifications.
Implement high-performance algorithms for clustering, min cost tree covering, and logic synthesis.
Develop C++ software to optimize large-scale RTL quality, timing, and power.
Drive the hardware design productivity roadmap by identifying and solving new optimization opportunities.
Work directly with design teams to facilitate the deployment of CAD tools and solutions.

What we're looking for

MS or PhD in Electrical Engineering, Computer Science, or equivalent experience.
3+ years of relevant experience in CAD software and VLSI hardware design.
Demonstrated ability in C++ software development, specifically for graph traversal, pattern matching, and optimization algorithms.
Familiarity with RTL design using Verilog and SystemVerilog.
Knowledge of hardware design concerns including scan chain insertion, MBIST, clock/power distribution, and bus architectures.
Familiarity with EDA techniques such as logic synthesis, global route, static timing analysis, and SAT solvers.
Experience with machine learning techniques like LLMs, GNNs, GANs, and Reinforcement Learning for optimization or code generation.
Strong communication and interpersonal skills.

Similar roles

CPU Core RTL Design Engineer

Amd

Austin, TX 64 days ago $178,400–$267,600

Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route

Hybrid

Save

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800

RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis

2+ yrs exp

Save

Processor Micro Architect RTL Design Engineer

Qualcomm

San Diego, CA 87 days ago $180,400–$270,600

RTL Verilog System Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Low Power Design Microprocessor Architecture Cache Bus Protocol Linting Clock Domain Crossing GDS2 Synthesis Simulation Regression

6+ yrs exp

Save

Senior Software R&D Engineer, ECO Route - VLSI EDA

Nvidia

Santa Clara, CA +1 11 days ago $168,000–$264,500

C++ EDA Physical Design Routing Algorithms Machine Learning SAT Solvers LLMs Reinforcement Learning GNNs Combinatorial Optimization Data Structures Algorithm Development DFT IR Drop Reduction Logic Synthesis Power Distribution Parallel Computing

5+ yrs exp

Save

CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 12 days ago $167,100–$250,700

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Waveform Debugging Simulators Power Management Functional Verification Hardware Engineering Firmware

4+ yrs exp

Save

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 12 days ago $142,200–$213,400

RISCV RTL Design Verilog VHDL Microarchitecture Logic Design Power Management Python Perl Waveform Debugging Simulators Hardware Engineering System Architecture

2+ yrs exp

Save