Software R&D Engineer, RTL Optimization Tools

Nvidia

Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Posted
5 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $173k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 57% of similar roles. Most pay $142,450–$203,200 — the shaded band above. At the midpoint, this role pays about $177k versus about $173k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 980 open roles on FindRole.

Listed pay typically runs $168,000–$270,250 across 966 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Software R&D Engineer, RTL Optimization Tools

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Join our dynamic team as a CAD Software Engineer at NVIDIA, where you will develop cutting-edge EDA tools by integrating parallel computing, machine learning, and novel algorithms in C++. Your role involves inventing new methods for parallel RTL analysis and manipulation, devising strategies to optimize data path latency and power consumption, and exploring the use of advanced AI techniques like GNNs and Reinforcement Learning. You will work closely with design teams to facilitate deployment and actively drive the roadmap for increasing hardware design productivity. Ideal candidates have a MS or PhD in Electrical Engineering or Computer Science, 3+ years of relevant experience, and expertise in C++ algorithm development, RTL design, and EDA techniques such as logic synthesis and static timing analysis. Experience with machine learning for optimization is also crucial.

Skills

C++ EDA RTL Verilog SystemVerilog DFT Clock_Distribution Power_Gating LLM GNN GAN Reinforcement_Learning Logic_Synthesis Static_Timing_Analysis SAT_Solvers Verific Espresso CI/CD

What you'll do

  • Invent new methods for parallel, graph-based RTL traversal and manipulation.
  • Devise strategies to analyze impact of RTL changes on latency, power, and DFT.
  • Explore use of LLMs, GNNs, GANs, and Reinforcement Learning for RTL modifications.
  • Develop high-performance clustering algorithms for efficient logic synthesis.
  • Work directly with design teams to facilitate deployment of optimization solutions.

What we're looking for

  • MS or PhD in Electrical Engineering or Computer Science or equivalent experience
  • 3+ years of relevant CAD software and VLSI hardware design experience
  • Strong C++ skills for algorithm development in graph traversal and optimization
  • Proficiency with RTL design, including Verilog/SystemVerilog and EDA techniques
  • Experience with machine learning techniques for analysis and code generation
  • Familiarity with common EDA building blocks like Verific and Espresso tools

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