below marketmost similar roles pay hereabove market
This role pays less than
64%
of similar roles. Most pay
$162,000–$223,000
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$192k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
The Software R&D Engineer, RTL Optimization Tools joins a team developing internal EDA tools by fusing parallel computing, machine learning, and novel algorithms in C++. You will invent methods for parallel, graph-based RTL traversal and analysis while devising strategies to evaluate the impact of RTL changes on data path latency, power, and DFT. Key responsibilities include exploring LLMs, GNNs, GANs, and Reinforcement Learning for automatic RTL modifications and developing high-performance algorithms for clustering, min cost tree covering, and logic synthesis. The role requires proficiency in C++, Verilog, and SystemVerilog, alongside knowledge of static timing analysis, SAT solvers, and SOC integration aspects like clock distribution and power gating. You will drive the roadmap for hardware design productivity by owning the full process from discovery to deployment.
Invent new methods for parallel, graph-based RTL traversal, analysis, and manipulation.
Analyze the impact of RTL changes on data path latency, power, and DFT/clocking.
Explore LLMs, GNNs, GANs, and Reinforcement Learning for automated RTL modifications.
Develop high-performance algorithms for clustering, min cost tree covering, and logic synthesis.
Own the full process from discovering optimization opportunities to developing and deploying solutions.
Drive the hardware design roadmap to increase productivity for design teams.
Write high-performance C++ code for graph traversal, pattern matching, and optimization.
What we're looking for
MS or PhD in Electrical Engineering or Computer Science or equivalent experience.
3+ years of relevant experience in CAD software and VLSI hardware design.
Demonstrated ability in software development with C++, particularly in algorithm development for graph traversal, pattern matching, and optimization.
Familiarity with RTL design, including Verilog and SystemVerilog, and hardware concerns like scan chain insertion, MBIST, and clock/power distribution.
Familiarity with EDA techniques including logic synthesis, global route, static timing analysis, and SAT solvers.
Strong communication and interpersonal skills.
Experience with common EDA building blocks such as Verific, Espresso, and various components for logic rewriting or combinatorial optimization (preferred).
Experience in high performance software design including multithreading, distributed computing, and efficient memory and I/O use (preferred).