PST Validation Engineer

Qualcomm

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$98,500–$147,700 / yr
Posted
78 days ago
Freshness
Confirmed live yesterday
Closes
Dec 22, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $170k
This role $123k
$85k most similar roles pay here $220k

This role pays less than 86% of similar roles. Most pay $141,464–$198,431 — the shaded band above. At the midpoint, this role pays about $123k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · PST Validation Engineer

As a PST Validation Engineer within the ASICS Engineering team, you will focus on post-silicon validation and emulation for high-performance, low-power products. Your daily responsibilities include performing silicon bring-up, measuring Vmin/Fmax, power, and thermal data across various PVTs to characterize SoC IPs at the system level. You will debug low-level hardware and software issues using JTAG and kernel debuggers like Lauterbach Trace32 while managing emulation builds to identify performance failures in collaboration with CAD, RTL, and Design teams. The role requires proficiency in C and Python for automating validation flows and data collection. Essential skills include an understanding of mobile chip architecture, including CPU, GPU, DDR, and NOCs, along with experience in designing test bench infrastructure for SoC emulation across different platforms to solve complex integration challenges.

What you'll do

  • Perform silicon bring-up and measure Vmin/Fmax, power, and thermal data across various PVTs and SoC IPs.
  • Debug low-level software and hardware issues using JTAG and kernel debuggers like Lauterbach Trace32.
  • Manage emulation builds to identify failures and performance issues in collaboration with CAD, RTL, and Design teams.
  • Automate validation flows, data collection, and analysis processes using Python or other scripting languages.
  • Develop test bench infrastructure for CPU/SoC emulation across different platforms.
  • Characterize and analyze system-level metrics for high-performance, low-power products.

What we're looking for

  • A Bachelor's degree in Science, Engineering, or a related field is required.
  • A Master's degree in Science, Engineering, or a related field is accepted as an alternative to the Bachelor's.
  • A PhD in Science, Engineering, or a related field is also accepted as an alternative qualification.
  • Candidates with a Bachelor's degree must have 2+ years of experience in ASIC design, verification, validation, or integration.
  • Candidates with a Master's degree must have 1+ year of experience in ASIC design, verification, validation, or integration.
  • Experience is required in debugging low-level software and hardware issues using tools like JTAG and kernel debuggers.
  • Proficiency in programming and scripting languages such as C and Python is required.
  • Knowledge of mobile chip architecture, basic RTL, and transistor power fundamentals is required.

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