Senior Silicon Architect, Cache Coherent Interconnects

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TXHillsboro, OR
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $219k

This role $216k

$155k $287k

below market most similar roles pay here above market

This role pays less than 53% of similar roles. Most pay $187,250–$250,812 — the blue band above. At the midpoint, this role pays about $216k versus about $219k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1792 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1179 roles with salary data.

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At a glance

TL;DR · Senior Silicon Architect, Cache Coherent Interconnects

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As a Senior Silicon Architect – Cache Coherent Interconnects, you will join the CPU Cache Coherent Interconnects Design Team to own the silicon architecture and construction plan for next-generation CPU processors. Your daily responsibilities include exploring 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions while managing dielet partitioning, packaging, and die-stacking exploration. You will develop early floorplans and plan die-to-die and off-chip IO, specifically focusing on UCIe, DRAM, and PCIe. The role requires expertise in digital design, CPU system architecture, ASIC floor-planning, and cache coherency. You must understand wire densities, TSMC InFO, CoWoS, Intel EMIB, through-silicon via configurations, and backside power delivery. This position solves complex hardware problems regarding area, performance, power, and thermal goals for high-performance semiconductor designs.

Skills

Digital Design ASIC Floor-planning Cache Coherency High-speed Interconnects UCIe DRAM PCIe 2.5D Interposer TSMC InFO CoWoS Intel EMIB Through-Silicon Via Backside Power Delivery NOC Logic Design Physical Design

What you'll do

Own the silicon architecture and construction plan for next-generation CPU processors.
Explore 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions.
Manage the placement of IO and compute components across various dielets.
Develop early floorplans for CPU cores, caches, and Network-on-Chip (NOC).
Plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe.
Achieve specific area, performance, power, and thermal goals through cross-functional coordination.

What we're looking for

Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.
8+ years of experience in processor or other related high-performance semiconductor designs.
Deep understanding of digital design, CPU system architecture, and ASIC floor-planning.
Knowledge of wire densities on-die and across 3D connected dies.
Strong background in cache coherency or high-speed interconnects and industry-standard protocols (preferred).
Knowledge of advanced packaging, through-silicon via configurations, and backside power delivery (preferred).
Strong communication and interpersonal skills.
Ability to work in a dynamic, global team.

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