Senior Signal Integrity Engineer, LPU Packaging

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $216k

$125k most similar roles pay here $279k

This role pays more than 83% of similar roles. Most pay $158,825–$208,800 — the shaded band above. At the midpoint, this role pays about $216k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Signal Integrity Engineer, LPU Packaging

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The Senior Signal Integrity Engineer joins the Packaging and Systems team to drive high-speed SerDes channel design, simulation, and correlation for advanced packages and data center platforms. This role involves leading signal integrity analysis across die, package, board, connector, socket, and cable interfaces while developing simulation flows for 2.5D, 3D, and multi-die integration. The engineer will optimize chip-package-board co-simulation methodologies, perform pre-layout and post-layout analyses, and correlate simulation with lab measurements using TDR, VNA, and oscilloscopes. Key technical requirements include expertise in electromagnetics, transmission line theory, NRZ and PAM4 signaling, and tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, and HSPICE. The role addresses critical signal integrity challenges for high-performance computing and AI applications, ensuring robust interconnect solutions across complex hardware structures like interposers, substrates, and various package escapes.

Skills

Signal Integrity SerDes Ansys HFSS SIwave Cadence Sigrity ADS HSPICE TDR VNA Oscilloscope IBIS-AMI S-parameters PAM4 NRZ PCIe CXL NVLink Ethernet

What you'll do

Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, and connector interfaces.
Develop and execute simulation flows for advanced packaging technologies including 2.5D, 3D, and multi-die integration.
Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems.
Perform pre-layout and post-layout signal integrity analysis to ensure electrical performance targets are met.
Correlate simulation results with lab measurements using TDR, VNA, and oscilloscopes to improve model accuracy.
Support interface bring-up, debug, and margin analysis for high-speed interconnect solutions.
Automate analysis, data processing, and visualization to scale SI methodology across multiple programs.

What we're looking for

BS, MS, or PhD in Electrical Engineering or equivalent experience.
8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles.
Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior.
Proven experience with high-speed SerDes design and analysis for advanced packaging and large-scale system applications.
Hands-on experience with industry-standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, or HSPICE.
Experience building and using channel models, S-parameters, IBIS-AMI based flows, and time/frequency-domain analysis techniques.
Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets.
Experience with simulation-to-measurement correlation and lab-based model validation using VNA, TDR, and high-speed scope measurements.

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