Senior Product Development Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$212,750 / yr
Employment
Full-time
Posted
108 days ago
Freshness
Confirmed live today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k
This role $174k
$125k most similar roles pay here $238k

This role pays less than 60% of similar roles. Most pay $159,750–$206,587 — the shaded band above. At the midpoint, this role pays about $174k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Product Development Engineer

As a Senior Product Development Engineer, you will join the team to drive the bring-up of state-of-the-art SOCs through collaboration with external vendors and internal design and production teams. Your daily responsibilities include leading wafer-level and package-level NPI bring-up for silicon programs, performing first silicon debug, characterization, and yield ramp. You will serve as the primary technical interface between ATE and internal partners to align on test strategy, DFT coverage, and engineering failure analysis. The role involves defining characterization plans for scan, mbist, IObist, and functional tests while analyzing product yield limiters. You will utilize skills in troubleshooting test failures, porting functional workloads to automated environments, and understanding software-hardware dependencies. Experience with Teradyne and Advantest platforms is a plus as you address technical challenges in the microelectronics and integrated circuits domain.

What you'll do

  • Lead wafer-level and package-level NPI bring-up for silicon programs including first silicon debug and characterization.
  • Serve as the primary technical interface between ATE and internal partners for test strategy and silicon qualification.
  • Define and drive silicon characterization plans covering scan, mbist, IObist, and functional tests.
  • Analyze product yield limiters and resolve failures on Automatic Test Equipment at wafer and package levels.
  • Characterize performance and power metrics to ensure competitive products reach the market.
  • Lead multi-functional efforts with design, foundry, and suppliers to root-cause problems and implement improvements.
  • Influence next-generation products by collaborating with architecture, software, and test teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering or equivalent experience.
  • 5+ years of relevant experience.
  • Analytical and problem-solving skills for troubleshooting test failures and optimizing coverage.
  • Experience porting functional workloads to an automated test environment.
  • Understanding of software-hardware dependencies.
  • Exposure to both Teradyne and Advantest platforms (preferred).

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