Senior Product Development Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$212,750 / yr
Employment
Full-time
Posted
106 days ago
Freshness
Confirmed live today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k
This role $174k
$125k most similar roles pay here $236k

This role pays less than 59% of similar roles. Most pay $157,375–$213,375 — the shaded band above. At the midpoint, this role pays about $174k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1388 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1103 roles with salary data.

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At a glance

TL;DR · Senior Product Development Engineer

As a Senior Product Development Engineer, you will join the team to drive the bring up of innovative SOCs through collaboration with external vendors and internal design and production teams. You will serve as the primary technical interface for test strategy, ATE bring-up, and silicon qualification while defining characterization plans for scan, mbist, IObist, and functional tests. Your daily responsibilities include ensuring robust test yields from NPI to high volume manufacturing, debugging yield distractors, and determining reliability stress conditions for embedded, commercial, industrial, and automotive needs. You will manage stress testing from wafer-level to package level and automate aging data from HTOL and DVS testing. Required expertise includes electrical engineering principles, root-cause analysis of ATE test failures, and experience with Teradyne or Advantest platforms to solve complex silicon qualification issues.

What you'll do

  • Serve as the primary technical interface between ATE and internal partners for test strategy and silicon qualification.
  • Define and drive silicon characterization plans covering scan, mbist, IObist, functional tests, and analog mixed-signal designs.
  • Debug and resolve test yield distractors systematically to achieve target yields from NPI to high volume manufacturing.
  • Determine reliability stress conditions based on product usage for embedded, commercial, industrial, and automotive needs.
  • Manage all aspects of silicon stress testing from wafer-level to package-level.
  • Evaluate, support, and deploy burn-in requirements during the NPI and MP phases.
  • Analyze and automate aging data from HTOL, package qualification, and DVS testing.
  • Drive true failures from reliability evaluation to final failure analysis reports in coordination with foundry teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering or equivalent experience.
  • 5+ years of relevant experience.
  • Analytical and problem-solving skills for root-cause analysis of ATE test failures.
  • Hands-on experience debugging chip-level failures on ATE platforms and driving failure analysis to closure.
  • Experience with SOC/Silicon qualifications including HTOL, ESD/LU, HTS, TC, and HAST.
  • Exposure to both Teradyne and Advantest platforms (preferred).

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