Senior Principal SOC Power Lead

Arm Holdings

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Hybrid

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Work type: Hybrid
Location: Austin, TXSan Diego, CA
Posted: 6 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $198k

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About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

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At a glance

TL;DR · Senior Principal SOC Power Lead

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The Senior Principal SOC Power Lead joins the Power Attainment team to drive power analysis, modeling, and optimization for System-on-Chip solutions. This leader manages a small team of power engineers to achieve power convergence across pre- and post-silicon stages. Key responsibilities include developing power models, defining workflows to improve accuracy and turnaround time, and ensuring products meet performance-per-watt targets. The role requires expertise in RTL and Netlist based power analysis, sign-off flows, and ASIC design dependencies like mixed Vt design and power domain partitioning. Candidates must utilize EDA tools and verification environments including VCS, Questasim, Incisive, Veloce Strato, Palladium, and Zebu. Proficiency in Python for automation and knowledge of hardware low power features like clock gating and voltage scaling are also required.

Skills

RTL Netlist EDA Tools ASIC Design VCS Questasim Incisive Veloce Strato Palladium Zebu Python Voltage/Frequency Scaling Power Domain Partitioning Mixed Vt Design Simulation Emulation

What you'll do

Lead a team of power engineers to drive power analysis, modeling, and optimization for SoC solutions.
Manage pre- and post-silicon power convergence to achieve best-in-class power efficiency.
Perform RTL and Netlist based power analysis and sign-off flows using industry-standard EDA tools.
Develop accurate project plans and define workflows to improve power modeling accuracy and turnaround time.
Create workload scenarios in simulation and emulation environments to verify power performance.
Decompose SoC use-case power budgets into specific IP power budgets.
Mentor junior engineers and provide technical leadership across multiple projects.

What we're looking for

Demonstrate strong technical leadership and the ability to develop accurate project plans involving multiple teams.
Possess expertise in RTL and Netlist based power analysis, sign-off flows, and EDA tools.
Understand ASIC design dependencies on power efficiency, including technology nodes, mixed Vt design, and power domain partitioning.
Have confirmed experience driving multiple projects and mentoring junior engineers.
Possess verification experience creating workload scenarios in simulation and emulation environments like VCS or Palladium.
Exhibit excellent presentation, interpersonal, and communication skills to present technical content internally and externally.
Appreciate software use-cases and how they interact with hardware low power features (preferred).
Proficiency in Python for automation and modeling (preferred).

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