Senior Power Integrity Methodology CAD Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $196,000–$310,500 / yr
Employment: Full-time
Posted: 25 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $253k

$131k most similar roles pay here $330k

This role pays more than 79% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $253k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1371 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.

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At a glance

TL;DR · Senior Power Integrity Methodology CAD Engineer

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As a Senior Power Integrity Methodology CAD Engineer, you will join the team to develop physical design methodologies for rail analysis and signoff. You will be responsible for creating unique solutions for pioneering IR analysis and signoff required for chips, while crafting workflows and tool methodologies for power and noise analysis across multiple projects. The role requires expertise in EMIR flow methodology development, hierarchical design approaches, and shift-left methodologies for optimization and convergence earlier in the chip build cycle. You will utilize programming and scripting languages including TCL, Perl, Python, and C++ to automate analysis and improve tool features. This position focuses on solving complex power integrity challenges within the GPU and AI technology domain, requiring a strong understanding of all aspects of EMIR analysis to facilitate successful signoff with hardware and design teams.

Skills

EMIR Power Integrity Rail Analysis Signoff TCL Perl Python C++ CAD Hierarchical Design AI Tools

What you'll do

Develop physical design methodologies for rail analysis and signoff.
Create unique solutions for pioneering IR analysis and signoff for NVIDIA chips.
Craft workflows and tool methodologies for power and noise analysis across multiple projects.
Implement shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
Develop custom workflows from scratch to address complex engineering challenges.
Utilize programming languages like TCL, Perl, Python, and C++ to automate analysis and improve tool features.
Integrate AI tools to enhance capabilities within the power integrity domain.

What we're looking for

Master's degree or equivalent experience in Electrical Engineering or a related field.
Minimum 10+ years of experience in EMIR flow methodology development and support.
Strong understanding of all aspects of EMIR analysis and signoff.
Familiarity with hierarchical design approach and hierarchical signoff.
Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.
Strong interpersonal, communication, and teamwork skills to collaborate across hardware and design teams.
Experience crafting custom workflows from scratch (preferred); experience using AI tools to improve power integrity capabilities (preferred).

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