Senior Modem ATE Test Engineer

Amazon Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CARedmond, WASan Diego, CA
Salary: $159,200–$215,300 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $164k

This role $187k

$131k most similar roles pay here $224k

This role pays more than 88% of similar roles. Most pay $149,887–$177,900 — the shaded band above. At the midpoint, this role pays about $187k versus about $164k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 467 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 456 roles with salary data.

Most-posted roles

View all roles at Amazon Inc

At a glance

TL;DR · Senior Modem ATE Test Engineer

Role Posting Log in to save

As a Senior Modem ATE Test Engineer, you will join the Amazon Leo team to develop high-volume production test methodologies for complex SoCs and modem devices powering a low-earth orbit satellite constellation. You will own end-to-end digital ATE test development on Advantest 93K and Teradyne UltraFLEX platforms, encompassing bring-up, pattern conversion, characterization, and production release. Your daily responsibilities include building and debugging scan/ATPG content, implementing MBIST and memory repair flows, and optimizing high-speed SERDES/HSIO tests including equalization and jitter characterization. You will also design and review final test and wafer sort hardware while analyzing production data using statistical methods like Cp/Cpk. The role requires expertise in JTAG, DFT principles, and scripting languages such as Python, Perl, and Tcl/Tk to ensure products are architected for cost-effective manufacturing in advanced process nodes.

Skills

Advantest 93K Teradyne UltraFLEX ATE DFT DFM Scan/ATPG MBIST SERDES HSIO JTAG Boundary-scan Python Perl Tcl/Tk JMP Wafer Sort Final Test PCB Design I3C SPI

What you'll do

Develop and debug digital test programs for complex ASIC/SoC and modem devices on Advantest or Teradyne platforms.
Build and debug scan/ATPG test content including stuck-at and transition fault models.
Implement MBIST and memory repair flows for high-volume production.
Optimize high-speed SERDES/HSIO tests, including equalization tuning and jitter characterization.
Convert DFT team patterns into tester-suitable formats and validate them on hardware.
Conduct silicon characterization to establish robust production limits and guard bands.
Design and review final test and wafer sort hardware for signal and power integrity.
Analyze production data using statistical methods to improve yield, quality, and test efficiency.

What we're looking for

Bachelor's degree or above in electrical engineering, computer engineering, or equivalent.
7+ years of experience in digital ATE test development and test engineering.
Experience testing complex SoCs and modem/wireless communication devices in advanced nodes (7nm and below).
Experience developing and debugging test programs on Advantest 93K and/or Teradyne UltraFLEX platforms.
Familiarity with JTAG, boundary-scan techniques, and DFT/DFM principles.
Proficiency in high-speed SERDES test at 100G+ including equalization tuning and jitter decomposition.
Experience with wafer sort and final test ATE hardware development, bring-up, and debugging.
Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.