Senior Modem ATE Test Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CARedmond, WASan Diego, CA
Salary: $185,200–$250,000 / yr
Posted: 50 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $168k

This role $218k

$131k $263k

below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $152,000–$184,300 — the blue band above. At the midpoint, this role pays about $218k versus about $168k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 648 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 642 roles with salary data.

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At a glance

TL;DR · Senior Modem ATE Test Engineer

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The Senior Modem ATE Test Engineer joins the Amazon Leo team to develop high-volume production test methodologies for custom silicon powering a low-earth orbit satellite constellation. This role involves leading the end-to-end digital ATE test development for complex SoCs and modem devices on Advantest 93K and Teradyne UltraFLEX platforms. Key responsibilities include developing and debugging scan/ATPG, MBIST, and memory repair content, as well as high-speed SERDES/HSIO testing for 100G+ interfaces. The engineer will perform silicon characterization, convert test patterns from STIL/WGL formats, and design hardware like load boards and probe cards. Required skills include proficiency in JTAG, DFT/DFM principles, and statistical data analysis using tools like JMP. The work addresses technical challenges in advanced process nodes to ensure cost-effective manufacturing of satellite communication hardware.

Skills

ATE Advantest 93K Teradyne UltraFLEX DFT DFM Scan ATPG MBIST SERDES HSIO JTAG STIL WGL Python Perl Tcl/Tk JMP I3C SPI GPIO Cp/Cpk Yield Analysis

What you'll do

Develop, debug, and release digital test programs for complex ASIC/SoC and modem devices on Advantest 93K and Teradyne UltraFLEX platforms.
Build and debug scan/ATPG test content, including stuck-at, transition, and other fault models.
Implement MBIST and memory repair flows for modem and ASIC devices.
Optimize high-speed SERDES/HSIO tests, including equalization, jitter/eye characterization, and BER.
Convert test patterns from DFT teams into tester-suitable formats and validate them on hardware.
Characterize silicon performance and process variation through ring oscillator and process monitor tests.
Design and review final test and wafer sort hardware, including load boards, sockets, and probe cards.
Analyze production data using statistical methods to drive continuous improvement in yield and test efficiency.

What we're looking for

Bachelor's degree or above in electrical engineering, computer engineering, or equivalent.
7+ years of experience in digital ATE test development and test engineering, preferably in high-volume manufacturing.
Experience testing complex SoCs and modem/wireless communication devices in advanced nodes (7nm and below).
Experience developing and debugging test programs on Advantest 93K and/or Teradyne UltraFLEX platforms.
Familiarity with JTAG and boundary-scan techniques, and with DFT/DFM principles.
Experience with digital test methodologies such as scan/ATPG, MBIST, Vmin search, and loopback.
Proficiency in advanced high-speed SERDES test at 100G+, including equalization tuning and jitter decomposition.
Export Control Requirement.