Senior Manager - Analog Design

Amd

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Boxborough, MA
Salary
$200,000–$300,000 / yr
Posted
85 days ago
Freshness
Confirmed live 2 days ago
Closes
May 22, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $250k
$133k most similar roles pay here $318k

This role pays more than 85% of similar roles. Most pay $172,000–$229,212 — the shaded band above. At the midpoint, this role pays about $250k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Manager - Analog Design

As a Senior Manager - Analog Design, you will lead the Memory I/O design team to define, specify, and implement future LPDDR IPs. You will manage the circuit architecture and design of high-speed analog and digital blocks while defining specifications for high-speed data paths and algorithms for calibration and equalization. Your daily work involves developing abstracted models for link performance simulations, documenting micro-architecture, and guiding cross-functional teams across Analog Mixed Signal, Digital, Firmware, and Verification to ensure optimal PHY architecture implementation. You will utilize industry-standard tools including Matlab, Simulink, and Verilog/AMS-based modeling. The role focuses on solving technical challenges in high-speed IO, specifically involving signal integrity, power integrity, and the development of area-efficient, low-power circuits for LPDDR PHYs to ensure successful silicon results across multiple complex designs.

What you'll do

  • Manage the design team responsible for defining and implementing circuit architectures for LPDDR IPs.
  • Define specifications for high-speed data paths, including calibration and equalization algorithms.
  • Develop abstracted models for link performance simulations to optimize design and development.
  • Coordinate with Analog Mixed Signal, Digital, Firmware, and Verification teams to ensure optimal PHY architecture implementation.
  • Manage project execution and deliverables across various customers and internal stakeholders.
  • Document micro-architecture and algorithms while providing technical guidance to cross-functional engineering teams.
  • Define and improve development flows to enhance the quality and efficiency of execution.

What we're looking for

  • Bachelor's, Master's, or Ph.D. degree in computer engineering or Electrical Engineering.
  • Minimum 5+ years of team management experience leading multiple IPs from design to production.
  • Proven track record of successfully leading execution of multiple PHY designs with high-quality silicon results.
  • Proven track record in circuit architecture and modeling for High Speed IOs.
  • Solid, hands-on knowledge of algorithms and equalization, calibration, and clocking techniques for high-speed circuit design.
  • Knowledge of industry-standard tools and best practices for PHY modeling using Matlab/Simulink or Verilog/AMS.
  • Good knowledge of IO and system integration including signaling, equalization, signal integrity, and power integrity.
  • Ability to analyze RTL or firmware code supporting custom circuit implementations.

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