Senior Analog Layout Engineer

What you'll do

• Build and optimize complex analog and mixed-signal layouts for 100G–400G/lambda optical solutions.
• Execute the full silicon lifecycle from initial floorplanning through post-layout extraction and tapeout.
• Manage block-to-top integration for next-generation optical interconnect architectures.
• Resolve complex parasitic, signal integrity, and thermal tradeoffs during the design process.
• Perform physical verification including DRC, LVS, ERC, and EM/IR analysis.
• Develop scripts in Python, Perl, or TCL to automate layout processes.
• Mentor junior engineering talent and establish design methodologies for the physical execution group.
• Conduct post-silicon bring-up to validate layout designs and hardware performance.

What we're looking for

• Bachelor's degree plus 7 years of related experience, Master's plus 4 years, or PhD plus 1 year of related experience.
• Prior experience supporting block-level layout efforts through tapeout.
• Prior experience in physical verification and custom layout design, specifically with custom analog layout in FINFET 7nm, 5nm, or 3nm.
• Prior experience with Cadence Virtuoso or similar custom layout tools.
• Prior experience in device-level layout techniques and critical design concepts like parasitic control and thermal management (preferred).
• Custom analog experience in TSMC 2nm or below (preferred).
• Prior experience with EDA tools like Cadence Virtuoso and Calibre in a Linux environment with a command of physical signoff flows (preferred).
• Prior experience with ASIC/SoC tapeout processes and scripting capabilities in Python, Perl, or TCL (preferred).