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Senior IC Layout Design Engineer

Amd

San Jose, CA 19 days ago $156,480–$234,720
Actively hiring Confirmed live today High trust Competitive pay
analog/mixed-signal layout SerDes CMOS Fin-FET LVS DRC ERC ANT ESD Cadence SKILL Python Perl Tcl IC Manufacturing Physical Design Verification Floor-planning Power Distribution Network Clock and Signal Routing

Senior Photonic Layout Design Engineer

Nvidia

Santa Clara, CA 49 days ago $148,000–$235,750
Actively hiring Confirmed live today High trust Competitive pay
Silicon Photonics Cadence Virtuoso DRC LVS Python SKILL Perl TCL C++ Calibre Waveguide Routing Tape-out CMOS Pcells ICV Dracula Primeyield Hercules SDL
10+ yrs exp