Senior Solutions Engineer FPGA/PCIe

Amd

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$200,000–$300,000 / yr
Posted
16 days ago
Freshness
Confirmed live 2 days ago
Closes
Sep 9, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $250k
$138k most similar roles pay here $317k

This role pays more than 91% of similar roles. Most pay $168,175–$216,250 — the shaded band above. At the midpoint, this role pays about $250k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 394 open roles on FindRole.

Listed pay typically runs $164,000–$246,000 across 394 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Senior Solutions Engineer FPGA/PCIe

As a Sr Solutions Engineer-FPGA/PCIe, you will join the team to architect and develop hardware and software co-design solutions for ASIC and FPGA based acceleration across networking, storage, automotive, aerospace, and AI workloads. You will participate in all phases of the product development cycle, including architecture, RTL development, pre-silicon verification, and post-silicon validation. Your daily work involves designing high-performance logic using SystemVerilog and Verilog for PCIe Gen 6/7, CXL, UAL, Ethernet, and DDR5/6. You will utilize the Vivado ecosystem to integrate custom IP with subsystems while performing hardware debugging in a lab environment. Required skills include expertise in synchronous design, timing closure, and UVM-based verification frameworks. Additionally, you will use Python, Tcl, Makefiles, and Shell scripting for automation to ensure functional correctness across complex embedded software and hardware fabrics.

What does a Solutions Engineer earn?

Median $173750 from 34 postings across 14 companies.

See salary data

What you'll do

  • Architect and develop hardware/software co-design solutions for ASIC and FPGA-based acceleration.
  • Design, verify, and validate high-performance logic using SystemVerilog and Verilog.
  • Implement designs for PCIe (Gen 6/7), CXL, UAL, Ethernet, and DDR5/6 protocols.
  • Integrate custom IP with other subsystems using standard ASIC flows and Vivado ecosystems.
  • Perform pre-silicon verification and emulation to ensure functional correctness and performance.
  • Lead the "Bring-up" process in the lab for post-silicon validation.
  • Debug complex interactions between embedded software and hardware fabric.
  • Develop automation scripts using Python, Tcl, Makefiles, and Shell scripting.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Experience designing, verifying, and validating high-performance logic using SystemVerilog/Verilog.
  • Ability to perform pre-silicon verification and post-silicon validation including lab bring-up and debugging.
  • Proficiency in Python, Tcl, Makefiles, and Shell scripting for automation (preferred).
  • Hands-on experience with ASIC/FPGAs (preferred).
  • Expertise in SystemVerilog/Verilog, synchronous design, and timing closure for high-speed logic (preferred).
  • Knowledge of PCIe, AXI, DDR, and Ethernet; familiarity with CXL or UAL is highly desirable (preferred).
  • Familiarity with UVM-based verification frameworks and emulation platforms like Palladium, Protium, or Zebu (preferred).

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