CPU Physical Design and Integration Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 100 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $203k

This role $162k

$113k most similar roles pay here $279k

This role pays less than 76% of similar roles. Most pay $167,375–$238,787 — the shaded band above. At the midpoint, this role pays about $162k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · CPU Physical Design and Integration Engineer

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The CPU Physical Design and Integration Engineer joins the hardware team to participate in the physical design, integration, and verification of high performance, low power processor development. This role involves critical tasks such as block partitioning, pin placements, chip level place and route, final CPU layout database construction, and physical verification. The engineer will collaborate with Implementation, CAD, and SOC teams to drive signoff closure for tapeout while participating in flow development for chip integration and analysis. Key technical requirements include experience with place and route, physical verification, and scripting languages like Perl or Tcl, with preferred knowledge of Python, CMOS circuit design, layout design, extraction, STA, and EMIR concepts. The role focuses on solving complex hardware challenges to ensure functional products are delivered efficiently through automated tasks and genAI initiatives.

Skills

Place and Route Physical Design DRC LVS STA EMIR Python Perl Tcl CMOS Layout Design tapeout GenAI Scripting

What you'll do

Perform block partitioning and pin placements for processor designs.
Manage chip-level place and route (PnR) processes.
Construct and verify the final CPU layout database.
Drive signoff closure for tapeout in coordination with Implementation and CAD teams.
Meet IP technical and delivery requirements in collaboration with the SOC team.
Develop flows for chip integration and analysis.
Write scripts to automate tasks, improve debug efficiency, and support genAI initiatives.

What we're looking for

Minimum BS degree.
Experience with place and route and physical verification.
Experience with a scripting language such as Perl or Tcl.
Knowledge of industry standard place and route tools and practices in physical design (preferred).
Fundamentals of physical construction, PDV, DRC/LVS verification (preferred).
Working knowledge of Python (preferred).
Understanding of CMOS circuit design (preferred).
Layout design background, extraction, STA, EMIR concepts, and team collaboration skills (preferred).

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