Senior DFT Engineer

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 8 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k

This role $216k

$127k most similar roles pay here $279k

This role pays more than 85% of similar roles. Most pay $155,925–$213,375 — the shaded band above. At the midpoint, this role pays about $216k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 980 open roles on FindRole.

Listed pay typically runs $168,000–$270,250 across 966 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior DFT Engineer

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As a senior Design-for-Test (DFT) Engineer at NVIDIA, you will lead cross-functional teams to implement cutting-edge test access mechanisms, IO BIST, memory BIST, and scan compression for complex semiconductor chips. You will develop and deploy DFT methodologies for next-generation products while mentoring junior engineers on test design trade-offs. This role requires a BSEE with 8+ years or MSEE with 5+ years of experience in DFT, expertise in defining scan test plans, fault modeling, ATPG, and verification using vendor tools. Strong skills in Perl, Python, or Tcl are desired, along with knowledge of RTL design, place-and-route, power management, and silicon debug on ATE systems. NVIDIA’s technology powers groundbreaking compute platforms used by scientists and engineers worldwide, enabling energy-efficient computing experiences for demanding users.

Skills

Perl Python Tcl Verilog VHDL DFT BIST ATPG fault simulation RTL design STA place-n-route power analysis Silicon debug ATE pattern formats failure processing test program development

What you'll do

Develop state-of-the-art test access mechanisms for complex semiconductor chips.
Implement innovative DFT methodologies for next-generation products.
Mentor junior engineers on test design principles and trade-offs.
Define scan test plans and BIST strategies for memory and IOs.
Analyze verification and validation of test patterns using vendor tools.

What we're looking for

BSEE with 8+ years, MSEE with 5+, or PhD with 3+ years in DFT or related fields.
Expertise in defining scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
Strong analytical skills for verification and validation of complex designs using vendor tools.
Experience in silicon debug and bring-up on ATE with pattern formats and failure processing knowledge.
Programming and scripting skills in Perl, Python, or Tcl desired.

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