Senior ASIC Verification Engineer

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 36 days ago

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Competitive pay

How this pay compares to similar roles

Similar $188k

This role $177k

$126k most similar roles pay here $228k

This role pays more than 54% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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NVIDIA is hiring a Senior ASIC Verification Engineer to join its cutting-edge team responsible for verifying the design and implementation of leading SoC's and GPU's. In this role, you will define verification scope, develop infrastructure, and create DV strategies and test plans for memory subsystem units, collaborating closely with designers and architects in feature discussions. The ideal candidate holds a Bachelors or Masters Degree in Electrical Engineering, Computer Science, or related field, with 4+ years of experience verifying complex chip units through tapeout. Proficiency in SystemVerilog/UVM, object-oriented programming principles, and verification techniques such as constrained random sequences and functional coverage is essential. Familiarity with memory subsystem concepts including consistency models, arbitration policies, and interface protocols is highly valued, along with a passion for delivering bug-free silicon and experience with AI tools and workflows.

Skills

SystemVerilog UVM Object-Oriented Programming Constrained Random Sequences Scoreboard Functional Coverage Memory Consistency Models Arbitration Policies Interface Protocols On-Chip Interconnect Caches xbar/Interconnect Fabric AI Tools Verification Methodologies

What you'll do

Define verification scope and develop infrastructure for complex SoC and GPU units.
Drive development of DV strategies and test-planning for memory subsystems.
Verify design, architecture, and micro-architecture using advanced verification methodologies.
Collaborate on feature and micro-architecture discussions with ASIC designers.
Develop scalable code using Object-Oriented Programming principles in SystemVerilog/UVM.

What we're looking for

4+ years of experience verifying complex units from start to tapeout for multiple chip generations.
Proficient in SystemVerilog/UVM and experienced in developing scalable verification code using OOP principles.
Expertise in advanced verification methodologies including constrained random sequences, scoreboards, and functional coverage.
Deep understanding of memory subsystem concepts such as consistency models, arbitration policies, and interface protocols.
Strong collaboration skills with ASIC designers and architects for feature and micro-architecture discussions.
Passionate about delivering bug-free first silicon and familiarity with AI tools and workflows.

Hybrid

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