RTL Design Engineer, Memory Controller

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $233k
$137k most similar roles pay here $282k

This role pays more than 76% of similar roles. Most pay $172,000–$231,300 — the shaded band above. At the midpoint, this role pays about $233k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

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View all roles at Arm Holdings

At a glance

TL;DR · RTL Design Engineer, Memory Controller

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As an RTL Design Engineer – Memory Controller, you will join the team to manage functional units of the Memory Controller while collaborating with performance modeling, validation, and implementation teams to meet specific PPA goals. Your daily responsibilities include developing high-level specifications, authoring detailed micro-architecture plans, and implementing SystemVerilog RTL logic for sophisticated blocks. You will also debug functional and performance issues using modern simulation tools. The role requires expertise in Verilog or VHDL, design synthesis, and tools for Lint, CDC, Power, and Synthesis checks. Candidates must possess knowledge of DRAM specifications such as LPDDR5, LPDDR6, DDR5, DDR6, and HBM3/4, alongside bus protocols like AMBA5 CHI, AMBA4 ACE, or AXI. This role focuses on the technical challenge of designing high-performance memory controller IP for complex SoC systems and interconnect architectures.

Skills

SystemVerilog RTL Design Verilog VHDL AMBA LPDDR5 DDR5 HBM3 SoC Memory Controller Synthesis Lint CDC PPA Micro-architecture Logic Design

What you'll do

  • Develop high-level specifications and requirements for Memory Controller products.
  • Author detailed micro-architecture plans for specific functional units.
  • Implement SystemVerilog RTL logic design for sophisticated blocks and functions.
  • Optimize designs to meet specific performance, power, and area (PPA) goals.
  • Debug functional and performance issues using modern simulation and debug tools.
  • Ensure design quality through Lint, CDC, Power, and Synthesis checks.

What we're looking for

  • Bachelor's or master's degree in Computer Science or Electrical/Computer Engineering.
  • 5+ years work experience in microprocessor, SoC, memory controller and/or interconnect IP design.
  • Prior RTL design experience is required.
  • Knowledge of DRAM specifications (e.g., LPDDR5, LPDDR6, DDR5, DDR6, HBM3/4) and bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI).
  • Experience with Verilog or VHDL and design synthesis to meet frequency, power, and area targets.
  • Experience with tools for RTL design quality checks such as Lint, CDC, Power, and Synthesis.
  • Prior Memory Controller RTL Design experience (preferred).
  • Prior verification or CAD experience, CPU/compute subsystem memory micro-architecture knowledge, and processor system knowledge (preferred).

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