RFIC Layout Engineer

What you'll do

• Perform transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
• Execute block-level layout through full verification flows including extraction, DRC, LVS, and DFM checking.
• Collaborate with designers to perform floorplanning for specific circuit blocks.
• Conduct layout reviews for power/ground routing and electromigration issues.
• Perform signal path checks, differential and IQ matching, and signal coupling analysis.
• Implement layout techniques for device matching, parasitic minimization, RF shielding, and high-frequency routing.

What we're looking for

• Bachelor's degree is required.
• Experience with FinFET technology is required.
• Experience in custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge (preferred).
• Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing (preferred).
• Solid understanding of RC delay, electromigration, and coupling (preferred).
• Understanding of guard rings, DNW, PN junctions, and advanced process effects like LOD and WPE (preferred).
• High level proficiency in interpreting CALIBRE DRC, ERC, and LVS in FinFet Technology (preferred).
• Knowledge of CADENCE layout tools and scripting skills in PERL or SKILL (preferred).