RFIC Layout Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $175,500–$311,700 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $244k

$131k most similar roles pay here $331k

This role pays more than 82% of similar roles. Most pay $168,500–$228,450 — the shaded band above. At the midpoint, this role pays about $244k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · RFIC Layout Engineer

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As an RFIC Layout Engineer, you will join the Wireless SoC Radio Team to design and bring next-generation wireless technologies into high-volume production using advanced CMOS technology nodes. You will perform detailed transistor-level layout for various RF and analog circuit blocks, including LNAs, mixers, PLLs, modulators, power amplifiers, and data converters like ADCs and DACs. Your daily responsibilities involve block level layout through full verification flows involving extraction, DRC, LVS, and DFM checking, alongside collaborating with designers on floorplanning. You will manage critical tasks such as power routing, electromigration checks, and signal path matching. The role requires expertise in FinFET technology, CADENCE tools, and scripting in PERL or SKILL. Key technical competencies include managing parasitics, RF shielding, high frequency routing, and advanced process effects like LOD and WPE.

Skills

RFIC Layout CMOS FinFET LNA Mixer PLL ADC DAC DRC LVS ERC DFM Cadence Perl SKILL RC Delay Electromigration high frequency routing

What you'll do

Perform detailed transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
Execute block-level layouts through full verification flows including extraction, DRC, LVS, and DFM checking.
Collaborate with designers to perform floorplanning for specific circuit blocks.
Conduct layout reviews for power/ground routing and electromigration issues.
Verify signal paths for differential and IQ matching while minimizing signal coupling.
Implement advanced layout techniques for device matching, RF shielding, and high-frequency routing.
Manage complex physical effects such as RC delay, guard rings, and deep sub-micron process effects.

What we're looking for

Bachelor of Science degree and 10+ years of relevant industry experience.
Experience with FinFET technology.
Experience in custom RF/analog layout for radio transceivers with knowledge of deep sub-micron CMOS (preferred).
Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing (preferred).
Solid understanding of RC delay, electromigration, and coupling (preferred).
Understanding of guard rings, DNW, PN junctions, and advanced process effects like LOD and WPE (preferred).
High level proficiency in interpreting CALIBRE DRC, ERC, and LVS in FinFET Technology (preferred).
Knowledge of CADENCE layout tools and scripting skills in PERL or SKILL (preferred).

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