RFIC Layout Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $118,019–$207,100 / yr
Posted: 20 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k

This role $163k

$104k most similar roles pay here $253k

This role pays less than 78% of similar roles. Most pay $168,425–$233,050 — the shaded band above. At the midpoint, this role pays about $163k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · RFIC Layout Engineer

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RFIC Layout Engineer As part of the wireless SOC organization, the RFIC Layout Engineer will perform detailed transistor-level layout for various analog and RF circuit blocks, including LNAs, mixers, PLLs, modulators, power amplifiers, and baseband filters. The role involves executing block-level and top-level floorplanning, managing schedules, and performing full verification flows including extraction, DRC, LVS, and DFM checking. Key responsibilities include reviewing layouts for electromigration, signal path checks, and differential matching while collaborating with designers to resolve failure-prone structures. Candidates should possess expertise in deep sub-micron CMOS, FinFET technology, and CADENCE layout tools. The role requires a strong understanding of RC delay, coupling, and high-frequency routing techniques. This position focuses on developing highly energy-efficient wireless silicon components to improve performance within complex integrated systems for advanced wireless communication products.

Skills

RF Layout Analog Layout FinFET CMOS Cadence Calibre DRC LVS ERC DFM Perl SKILL Floorplanning Electromigration RC Delay High-Frequency Routing

What you'll do

Perform transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
Execute block-level and top-level floorplanning in coordination with circuit designers.
Conduct layout reviews for power/ground routing, electromigration, signal path checks, and differential matching.
Perform full verification flows including extraction, DRC, LVS, and DFM checking.
Manage top-level layout integration and project scheduling.
Implement layout techniques to minimize parasitics, provide RF shielding, and ensure high-frequency routing.
Identify failure-prone circuit structures and proactively collaborate with designers to resolve issues.

What we're looking for

A bachelor's degree is required.
Must understand RC delay, electromigration, and coupling.
Ability to identify failure-prone circuit/layout structures and collaborate with designers to resolve issues.
Good communication skills and ability to work with multi-functional teams.
Experience in custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge (preferred).
Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing (preferred).
Understanding of guard rings, DNW, PN junctions, and sophisticated process effects like LOD and WPE (preferred).
Proficiency in CALIBRE DRC/ERC/LVS in FinFET technology, CADENCE tools, or scripting in PERL/SKILL (preferred).