RFIC Layout Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
15 days ago
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Confirmed live today

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Similar $201k
$140k most similar roles pay here $246k

This listing doesn't post a salary. Most similar roles pay $168,000–$233,050.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

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TL;DR · RFIC Layout Engineer

As an RFIC Layout Engineer, you will join the Wireless SoC Radio Team to design and bring next-generation wireless technologies into production using advanced CMOS technology nodes. You will work closely with the RFIC design team to perform detailed transistor-level layout and verification for complex SoC products. Your daily responsibilities include laying out various blocks such as LNAs, mixers, PLLs, power amplifiers, and data converters while performing floorplanning and verifying designs through extraction, DRC, LVS, and DFM checks. You will manage critical tasks like power routing, electromigration analysis, and signal coupling. The role requires expertise in FinFET technology, Cadence layout tools, and CALIBRE. Preferred skills include knowledge of RF shielding, high-frequency routing, and scripting in PERL or SKILL to address challenges in device matching and parasitic minimization within the radio transceiver domain.

What you'll do

  • Perform transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
  • Execute block-level layout through full verification flows including extraction, DRC, LVS, and DFM checking.
  • Collaborate with designers to perform floorplanning for complex SoC components.
  • Conduct layout reviews for power/ground routing and electromigration issues.
  • Verify signal paths for differential and IQ matching and minimize signal coupling.
  • Implement layout techniques for device matching, RF shielding, and high-frequency routing.
  • Manage advanced process effects such as LOD, WPE, guard rings, and PN junctions.

What we're looking for

  • Minimum of 5 years of related experience required.
  • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, and LVS in FinFET Technology.
  • Knowledge of Cadence layout tools.
  • Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing (preferred).
  • Solid understanding of RC delay, electromigration, and coupling (preferred).
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE (preferred).
  • Scripting skills in PERL or SKILL (preferred).

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