R&D Digital Design Engineer

What you'll do

• Write efficient and elegant RTL for implementing components of complex networking ASICs.
• Develop micro-architecture specifications based on technical requirements.
• Perform unit verification to ensure design accuracy.
• Achieve timing convergence for high-performance ASICs in deep submicron technologies.
• Implement ECOs and perform debug analysis during the design lifecycle.
• Implement low power design techniques and clock domain crossing methods.
• Develop logic for packet processing features like parsing, ACLs, metering, and policing.

What we're looking for

• B.S. in electrical engineering, computer engineering, computer science, or equivalent.
• B.S. with 8 years of experience or M.S. with 5 years of experience in digital design on multiple networking ASICs.
• At least 5 years of experience in Verilog based RTL design or verification in deep submicron technologies.
• Familiarity with Ethernet and other networking protocols.
• Extensive experience with Ethernet, TCP/IP, MPLS, tunneling, and other networking protocols.
• Experience with packet processing architectures including parsing, ACLs, metering, and policing.
• Experience achieving timing closure on high performance ASICs in deep submicron technologies.
• Experience with low power design techniques, power estimation methods, clock domain crossing, and scripting languages like Python or Perl.