Principal SoC Circuit Architect

Microsoft

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Salary
$142,800–$274,800 / yr
Posted
7 days ago
Freshness
Confirmed live yesterday
Closes
Mar 8, 2027

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Competitive pay

How this pay compares to similar roles

Similar $209k
This role $209k
$127k most similar roles pay here $291k

This role pays less than 51% of similar roles. Most pay $177,250–$240,000 — the shaded band above. At the midpoint, this role pays about $209k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 589 roles with salary data.

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At a glance

TL;DR · Principal SoC Circuit Architect

The Principal SoC Circuit Architect joins the AI SoC Development team to design and optimize hardware for cloud infrastructure. This role focuses on the high-level definition of SoC components, specifically targeting high-speed IO PHYs such as Ethernet, HBM4/4E/5, and D2D. The architect is responsible for overseeing signal and power integrity, defining end-to-end power delivery solutions, and establishing REFCLK and digital clocking methodologies through quality simulations. Additionally, the position involves collaborating with package and system design teams on SoC technology definitions and partnering with custom memory development teams to define new memory-related IPs. The role requires expertise in PLL and clocking solutions for AI SoCs, as well as familiarity with package/substrate and PCB design issues related to power delivery. This work addresses critical challenges in scaling and optimizing large-scale cloud hardware infrastructure.

What you'll do

  • Define SoC level high-speed IO PHYs including Ethernet, HBM4/4E/5, and D2D.
  • Supervise signal and power integrity for SoC designs.
  • Define and quality control end-to-end power delivery solutions.
  • Define SoC level REFCLK, digital clocking methodology, and perform quality simulations.
  • Partner with package and system design teams to define SoC technology specifications.
  • Define SoC memory architecture in collaboration with the custom memory development team.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Engineering, or Computer Science and 3+ years of technical engineering experience.
  • A Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of technical engineering experience.
  • A Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Ability to provide proof of citizenship, residency, or other protected status for export control compliance.
  • 15+ years of experience in SoC level Circuit architecture and design with an MSEE (preferred).
  • 12+ years of experience in SoC level Circuit architecture and design with a PhD (preferred).
  • Experience in PLL/Clocking solutions, High Speed IO PHY design, Signal Integrity, and PCB power delivery for AI SoCs (preferred).

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