Principal Engineer - Low Power Chip Architect / System Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$192,000–$288,000 / yr
Posted
2 days ago
Closes
Nov 29, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $240k
$138k most similar roles pay here $304k

This role pays more than 83% of similar roles. Most pay $168,500–$224,100 — the shaded band above. At the midpoint, this role pays about $240k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 615 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 556 roles with salary data.

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At a glance

TL;DR · Principal Engineer - Low Power Chip Architect / System Engineer

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Qualcomm Technologies is hiring a senior-level Low Power Chip Architect/ System Engineer to lead the development of ultra-low-power integrated circuits for Robotics and Industrial IoT applications in San Diego. This role involves defining system architecture, driving transistor-level design, and enabling integration across analog, digital, firmware, and system domains. The candidate will collaborate with cross-functional teams from concept definition through silicon bring-up, focusing on power, performance, noise, latency, and silicon area trade-offs. Key responsibilities include leading feasibility studies for mixed-signal building blocks like ADCs, DACs, PLLs/DLLs, LDOs, and SerDes, developing behavioral models using MATLAB/Simulink, and supporting post-silicon bring-up activities. The ideal candidate has a Ph.D. or M.S. in Electrical Engineering with extensive experience in low-power analog and mixed-signal IC design, proficiency in Cadence Virtuoso, AMS simulations, and digital design flows, and expertise in Python scripting and deep submicron CMOS technologies.

Skills

Cadence Virtuoso AMS sims Verilog Spectre HSPICE PDKs LVS DRC PEX Python I2C I3C SPI MIPI IC packaging board-level validation deep submicron CMOS technologies sensor systems sensor fusion edge AI applications firmware development digital design flows

What you'll do

  • Define and support end-to-end system architecture across multiple domains.
  • Drive architectural trade-offs to optimize power, performance, noise, latency, and silicon area.
  • Lead feasibility studies and transistor-level design of mixed-signal building blocks.
  • Architect ultra-low-power AFEs optimized for battery-operated IIoT and Robotics sensor ASICs.
  • Develop behavioral and system-level models using MATLAB/Simulink to evaluate circuit performance.

What we're looking for

  • Deep expertise in mixed-signal IC and system-level design.
  • Proven track record of chip-level technical leadership.
  • Strong hands-on experience with low-power analog and mixed-signal (AMS) IC design.
  • Extensive industry experience as a Chip Lead, System Architect, or Technical Lead.
  • Proficiency in Cadence Virtuoso, AMS simulations, Verilog, and related tools.
  • Ability to drive full-chip execution from concept through silicon bring-up.

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