Principal DFT Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type
On-site
Location
Austin, TX
Posted
today

Market check

Salary context

How this pay compares to similar roles

Similar $195k
$152k most similar roles pay here $238k

This listing doesn't post a salary. Most similar roles pay $168,500–$222,000.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal DFT Engineer (Silicon Engineering)

Apply Now Log in to save

The Principal DFT Engineer role at Silicon Engineering in Austin, TX, is a senior-level position responsible for leading the implementation and optimization of Design for Test (DFT) architectures. This includes managing scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools, as well as generating test patterns and providing post-silicon testing support. The candidate will work with RTL and gate netlist DFT implementation, integrate DFT fabrics within subsystems, and develop automated processes using Perl, Python, Tcl, or C+. Ideal candidates have extensive experience in ASIC design, scan insertion, and DFT setup, along with a deep understanding of UPF, formal verification, and advanced silicon process nodes.

Skills

Perl Python Tcl C++ Siemens_Tessent UPF Verilog SystemVerilog DRC ATPG SDF CI/CD

What you'll do

  • Lead implementation and optimization of DFT architectures using Siemens Tessent tools.
  • Own ATPG tools and methodologies, generating patterns for various fault models.
  • Evaluate design readiness for scan insertion through RTL and physical design Scan DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within Subsystems.
  • Develop test scripts and automate processes using programming languages like Perl or Python.

What we're looking for

  • 10+ years of experience in ASIC design and DFT setup, integration, and validation.
  • Leadership role in driving SOC DFT execution from concept to tapeout and product deployment.
  • Proficiency with Siemens Tessent tools for RTL and gate netlist DFT implementation.
  • Experience with UPF (Unified Power Format) and formal verification methodologies.
  • Strong skills in Verilog/SystemVerilog for design block integration and debugging.
  • Familiarity with advanced silicon process nodes, ATE testers, and test teams.

Related searches

More Principal DFT Engineer jobs Principal DFT Engineer jobs in Austin All jobs at SpaceX

More like this

Similar roles

Principal DFT Engineer (Silicon Engineering)

SpaceX

Irvine, CA today $200,000–$285,000
Siemens_Tessent Perl Python Tcl C++ Verilog SystemVerilog UPF DRC ATE_testers ASIC_design RTL_simulation Gate_level_simulation SDF_annotated_simulations Design_for_Test(DFT) Scan_insertion ATPG_tools Pattern_compression Hierarchical_test_flows
Save

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Austin, TX today
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test(IST) boundary_scan(IEEE_1149.1)
Save

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA today $125,000–$150,000
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG
Save

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Sunnyvale, CA today $135,000–$160,000
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test boundary_scan functional_testing board_level_diagnostics
Save

ASIC Engineering Technical Leader - DFT

Cisco

Remote (San Jose, CA) 63 days ago $183,800–$263,600
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis
Remote
Save