Pre-Silicon Digital Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$129,300–$194,700 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $162k
$117k $242k
below market most similar roles pay here above market

This role pays less than 79% of similar roles. Most pay $168,500–$227,500 — the blue band above. At the midpoint, this role pays about $162k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Pre-Silicon Digital Verification Engineer

Role Posting Log in to save

JOB TITLE: Pre-Silicon Digital Verification Engineer As a Pre-Silicon Digital Verification Engineer within the mixed signal ASIC team, you will verify complex digital IPs for custom integrated circuits. You will collaborate with system architects and digital designers to clarify block level specifications and develop comprehensive verification plans covering functional, performance, stress, and error conditions. Your daily responsibilities include creating verification testbenches, building testcases, and debugging failures to ensure bug-free designs for first tapeout. You will utilize System Verilog, UVM, and System Verilog Assertions to develop drivers, tests, reference models, and checkers. The role involves using formal verification, digital mixed signal verification, and analog mixed signal simulation. You will also track progress using functional and code coverage while participating in code reviews for various blocks across the chips.

Skills

System Verilog UVM Formal Verification Constrained Random Verification Mixed Signal Verification Digital Design Computer Architecture Object Oriented Programming Code Coverage ASIC Clock Domain Crossing Analog Circuit Design

What you'll do

  • Develop precise design specifications for digital control blocks with system architects and designers.
  • Create block and chip level verification plans to exercise functional, performance, and stress cases.
  • Build verification testbenches using formal verification and UVM based simulation.
  • Develop drivers, tests, reference models, and checkers using System Verilog and UVM.
  • Create testcases using System Verilog Assertions and constrained random UVM to achieve full coverage.
  • Debug test failures and work with designers to implement necessary fixes.
  • Use functional and code coverage to track progress and gauge tapeout readiness.
  • Participate in code reviews for other blocks to ensure bug-free designs.

What we're looking for

  • A minimum of a bachelor's degree in a related field.
  • Extensive course work in digital design and computer architecture (preferred).
  • Foundation in object oriented programming techniques (preferred).
  • Lab courses or work experience with System Verilog (preferred).
  • Familiarity with constrained random verification techniques (preferred).
  • Familiarity with clock domain crossing design and verification techniques (preferred).
  • Some course work in analog circuit design (preferred).

Related searches

More Pre jobs Pre jobs in Sunnyvale All jobs at Apple Inc

More like this

Similar roles

Pre-Silicon Digital Verification Engineer

Apple Inc

Sunnyvale, CA 5 days ago $150,400–$277,600
System Verilog UVM Formal Verification Constrained Random Verification Mixed Signal Verification Digital Design Computer Architecture Object Oriented Programming Code Coverage ASIC Clock Domain Crossing Analog Circuit Design
3+ yrs exp
Save

ASIC Verification Engineer

Nvidia

Santa Clara, CA 27 days ago $116,000–$189,750
System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics ASIC Design Verification Object-Oriented Programming Profiling Tools X prop
3+ yrs exp Hybrid
Save

Design Verification Engineer

Apple Inc

Cupertino, CA 44 days ago $150,400–$225,300
System Verilog Verilog UVM Python Perl VCS Verdi Indago Digital Design Computer Architecture Constrained Randomization Assertion Methodology ASIC SoC Mixed Signal
Save

Pre-Silicon Validation Engineer

Qualcomm

San Diego, CA 17 days ago $101,400–$152,200
SystemVerilog C/C++ Python ASIC Emulation FPGA Prototyping Linux Cadence Palladium Siemens Veloce Synopsys ZeBu RTL Verification SoC Verification Hardware/Software Co-Validation Shell Scripting PCIe CXL DDR Ethernet AI/ML
Save

Senior Staff Pre Silicon Verification Engineer

Amd

San Jose, CA 39 days ago $200,000–$300,000
System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Metric-Driven Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal NoC Silicon Debug Regression Management
8+ yrs exp
Save

Pre-Silicon Engineer

Apple Inc

Cupertino, CA 45 days ago $150,400–$277,600
Machine Learning Silicon Engineering Firmware Micro-architecture hardware bringup
Save