Pre-Silicon Digital Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $150,400–$277,600 / yr
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $214k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Pre-Silicon Digital Verification Engineer

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The Pre-Silicon Digital Verification Engineer joins the mixed signal ASIC team to verify complex digital IPs for custom integrated circuits. Working with system architects and digital designers, you will clarify block level specifications and build verification plans to exercise functional, performance, stress cases, and error conditions. You will own the creation of verification testbenches using formal verification and UVM based simulation. Your daily tasks include building testcases using System Verilog Assertions and constrained random UVM testcases to achieve complete functional and code coverage. You will also participate in code reviews and debug test failures. Key skills include System Verilog, UVM, object oriented programming, and knowledge of clock domain crossing design and digital mixed signal verification for mixed signal integrated circuits.

Skills

System Verilog UVM Formal Verification Constrained Random Verification Mixed Signal Verification Digital Design Computer Architecture Object Oriented Programming Code Coverage ASIC Clock Domain Crossing Analog Circuit Design

What you'll do

Develop precise design specifications for digital control blocks with system architects and designers.
Create block and chip level verification plans to exercise functional, performance, and stress cases.
Build verification testbenches using formal verification and UVM based simulation.
Develop drivers, tests, reference models, and checkers using System Verilog and UVM.
Create testcases using System Verilog Assertions and constrained random UVM techniques.
Debug test failures and work with designers to implement necessary fixes.
Track progress and gauge tapeout readiness using functional and code coverage metrics.
Participate in code reviews for various blocks to ensure bug-free designs.

What we're looking for

BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
Experience using System Verilog and UVM to develop drivers, tests, reference models, and checkers.
Ability to create block and chip level verification plans from design specifications.
Experience using functional and code coverage to track progress and gauge tapeout readiness.
Extensive course work in digital design and computer architecture (preferred).
Foundation in object oriented programming techniques (preferred).
Familiarity with constrained random verification, clock domain crossing, and analog circuit design (preferred).

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