PMU Design Verification Engineer: Analog & Mixed Signal Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$277,600 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 60% of similar roles. Most pay $177,200–$241,750 — the blue band above. At the midpoint, this role pays about $214k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3564 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2760 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · PMU Design Verification Engineer: Analog & Mixed Signal Engineer

Role Posting Log in to save

The PMU Design Verification Engineer: Analog & Mixed Signal Engineer joins the analog and mixed signal verification team to ensure high-quality silicon for IC chips and IPs. This role involves full-chip verification of mixed-signal systems, specifically focusing on power management and auxiliary circuitry like switching converters, linear converters, reference circuitry, bandgaps, data converters, and clock generators. Daily responsibilities include reviewing specifications, writing verification plans, developing test benches, running simulations, triaging issues, and signing off designs for tape-out. Candidates must use hardware descriptive languages including Verilog, SystemVerilog, and Verilog-AMS, along with scripting languages like TCL, Skill, Python, and PERL. The work requires proficiency in simulators, waveform viewers, and execution automation to verify mixed-signal designs using a combination of analog circuits and RTL in the same simulation.

Skills

mixed signal verification System-Verilog Verilog Verilog-AMS Python TCL Skill Perl RTL Gate Level Simulation Assertions Coverage Collection Waveform Viewers Compute Clusters

What you'll do

Develop detailed test and coverage plans based on IC specifications.
Build and bring up verification test benches and environments from scratch.
Create verification methodologies that ensure scalability and portability for IPs.
Develop stimuli, checkers, assertions, trackers, and coverage for mixed-signal designs.
Run simulations on compute clusters while optimizing simulation and wall time.
Triage issues and debug failures in analog and mixed-signal IC designs.
Sign off on mixed-signal designs in preparation for tape-out.

What we're looking for

BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
Ability to verify analog/mixed-signal designs in a collaborative team environment (preferred).
Proficiency in hardware descriptive languages including Verilog, SystemVerilog, and/or Verilog-AMS (preferred).
Familiarity with authoring analog assertion checks and identifying failure mechanisms in analog IC designs (preferred).
Ability to write test plans and communicate clearly with multi-functional teams (preferred).
Experience with simulation tools, waveform viewers, execution automation, and gate level simulations (preferred).
Background in scripting languages such as TCL, Skill, Python, or PERL (preferred).

Save