This role pays less than
58%
of similar roles. Most pay
$168,500–$241,750
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$205k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3513 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2730 roles with salary data.
As a Mixed Signal Verification Engineer within the Hardware Technology organization, you will be responsible for verifying the functionality and performance of premier SOCs. You will own the modeling and verification of advanced analog and RF blocks, such as regulators, bandgaps, data converters, LNAs, PAs, mixers, and PLLs. Your daily responsibilities include developing RNM models in SystemVerilog with self-checking techniques, creating assertions to ensure analog and digital specifications are met, and collaborating with analog designers to set up AMS simulation environments. You will also debug complex chip digital-on-top testbenches to identify root causes for failures. The role requires strong fundamentals in analog and RF circuit theory, proficiency in RNM coding using SystemVerilog, and experience with the Cadence mixed signal verification environment to solve critical integration challenges within large scale systems.
Develop RNM RF and analog models using SystemVerilog.
Create self-checking models for various analog and RF blocks within a large SoC.
Determine the required model accuracy levels based on specific verification goals.
Develop assertions to ensure analog and digital specifications are met.
Collaborate with analog designers to set up AMS simulation environments.
Debug complex chip digital-on-top testbenches to identify root causes for failures.
What we're looking for
A bachelor's degree is required.
Strong fundamentals in analog/RF circuit theory and topologies are required.
Experience with RNM coding in SystemVerilog is required.
An MS degree and at least 3 years of industry experience are preferred.
Experience working with Cadence mixed signal verification environment is preferred.
Ability to read analog schematics and extract related main functionality is preferred.
Experience modeling mixed signal/RF blocks including biasing networks, power regulators, bandgaps, Opamps, OTAs, data converters, LNAs, PAs, mixers, couplers, splitters, and combiners is preferred.
Experience modeling high frequency PLLs is desired.