Physical Design Engineer

As a Physical Design Engineer, you will join the hardware team to execute critical PHY design efforts in collaboration with architecture, CAD, timing, and logic design teams. You will manage all phases of physical design for high-performance PHY designs from RTL through final GDSII delivery. Your daily responsibilities include generating block and chip level static timing constraints, building full chip floorplans with pin placement and power grids, and developing low-power clock network guidelines. You will perform place and route to meet timing, area, and power constraints while implementing ECOs for noise and EM IR violations. The role requires expertise in physically aware synthesis, extraction, and STA methodology using industry standard tools. You must be proficient in Verilog, Perl, and Tcl to resolve timing issues and manage physical verification flows including LVS and DRC.