Physical Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 16 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $205k

$137k most similar roles pay here $274k

This listing doesn't post a salary. Most similar roles pay $168,500–$241,750.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will join the hardware team to execute critical physical design efforts for high-performance PHY designs from RTL through final GDSII delivery. You will collaborate with architecture, CAD, timing, and logic design teams to manage block and chip level tasks. Your daily responsibilities include generating static timing constraints, building full chip floorplans with pin placement and power grids, and developing low-power clock network guidelines. You will perform place and route to meet area and power constraints while implementing ECOs to resolve noise and EM IR violations. The role requires expertise in physically aware synthesis, extraction, and STA methodology. You must be proficient in Verilog, Perl, and Tcl scripting while utilizing industry standard physical design and synthesis tools to navigate complex SoC architecture and physical verification requirements.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

Physical Design RTL GDSII Floor-planning Place and Route STA Verilog Perl Tcl LVS DRC Synthesis Power Grid EM

What you'll do

Generate block and chip level static timing constraints.
Build full chip floorplans including pin placement, partitions, and power grids.
Develop and validate high performance, low power clock network guidelines.
Perform block level place and route to meet timing, area, and power constraints.
Implement ECOs to resolve timing, noise, and EM IR violations.
Execute physical design verification flows and provide guidance for LVS/DRC fixes.
Establish CAD and physical design methodologies for correct-by-construction designs.
Assist in developing flow processes for chip integration.

What we're looking for

Bachelor of Science in Electrical Engineering.
10 years of experience (preferred).
Deep design experience in high PHY and/or SOC designs (preferred).
Knowledge of industry standards in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route (preferred).
Experience developing and implementing Power-grid and Clock specifications (preferred).
Strong understanding of Physical construction, Integration, and Physical Verification (preferred).
Knowledge of Basic SoC Architecture and HDL languages like Verilog (preferred).
Proficiency in scripting languages such as Perl/Tcl and knowledge of Extraction and STA methodology (preferred).