Quick summary
- Work type
- On-site
- Location
- San Francisco, CA
- Salary
- $150,400–$277,600 / yr
- Posted
- 14 days ago
- Freshness
- Confirmed live 2 days ago
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
Competitive pay
How this pay compares to similar roles
Similar $203k
This role $214k
$135k
most similar roles pay here
$293k
This role pays more than 64% of similar roles. Most pay $168,500–$237,800 — the shaded band above. At the midpoint, this role pays about $214k versus about $203k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 2925 open roles on FindRole.
Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.
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At a glance
TL;DR · Physical Design Engineer
As a Physical Design Engineer, you will join a team focused on high-performance PHY design efforts, collaborating with architecture, CAD, timing, and logic design teams. You will manage the physical design process from RTL through final GDSII delivery. Your daily responsibilities include generating block and chip level static timing constraints, building full chip floorplans including pin placement and power grids, and developing low-power clock network guidelines. You will perform place and route to meet timing, area, and power constraints while implementing ECOs to resolve noise and EM IR violations. The role requires expertise in physical design verification for LVS/DRC issues, as well as proficiency in Verilog, Perl, and Tcl. You will also contribute to CAD methodologies and flow development for chip integration within the high-performance PHY and SoC domain.
Skills
What you'll do
- Generate block and chip level static timing constraints.
- Build full chip floorplans including pin placement, partitions, and power grids.
- Develop and validate high performance, low power clock network guidelines.
- Perform block level place and route to meet timing, area, and power constraints.
- Generate and implement ECOs to fix timing, noise, and EM IR violations.
- Run physical design verification flows and provide guidance to fix LVS/DRC violations.
- Establish CAD and physical design methodologies for correct by construction designs.
- Assist in flow development for chip integration.
What we're looking for
- Bachelor of Science in Electrical Engineering.
- 3+ years experience (preferred).
- Deep design experience in high PHY and/or SOC designs (preferred).
- Knowledge of industry standards in Physical Design, including physically aware synthesis, floor-planning, and place and route (preferred).
- Experience developing and implementing power-grid and clock specifications (preferred).
- Strong understanding of physical construction, integration, and physical verification (preferred).
- Knowledge of basic SoC architecture and HDL languages like Verilog (preferred).
- Proficiency in scripting languages such as Perl/Tcl and STA methodology (preferred).
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