PHY Design Verification Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 57 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k

This role $168k

$111k most similar roles pay here $233k

This role pays less than 69% of similar roles. Most pay $165,150–$214,500 — the shaded band above. At the midpoint, this role pays about $168k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · PHY Design Verification Engineer

Role Posting Log in to save

As a PHY Design Verification Engineer, you will join the wireless silicon development team to perform pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will collaborate with DV methodologists, designers, and systems engineers to develop reusable testbenches and verification environments using metric-driven methodologies. Your daily responsibilities include creating verification plans from specifications, developing directed and constrained random tests, managing bug tracking, and analyzing coverage models. The role involves utilizing advanced technologies including Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab/C reference models, and AI for data mining. You will also support PHY subsystem validation using Palladium and FPGA hardware. This position addresses the technical challenges of ensuring high design quality for wireless communication subsystems involving protocols such as Bluetooth, UWB, WLAN, or Zigbee.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion Python Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Bluetooth WLAN Zigbee UWB

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem test benches using best-in-class DV methodologies.
Develop and execute directed and constrained random tests for RTL verification.
Debug failures, manage bug tracking, and work with designers to resolve issues.
Create and analyze coverage models while adding test cases to increase coverage.
Utilize machine learning and AI technologies to identify design and test bench issues.
Support PHY subsystem validation using Palladium and FPGA platforms.
Improve DV methodology and flow through collaboration with team members.

What we're looking for

A bachelor's degree is required.
An MSEE with 2+ years of verification experience for wireless or wired communication blocks/subsystems is preferred.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion is required.
Experience in ASIC verification flows including test bench development, constrained random testing, and coverage analysis is required.
Proficiency in shell, Python, and Perl scripting is required.
Experience using Matlab/C reference models and bit-accurate verification is preferred.
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee is preferred.
Experience with Palladium/FPGA validation and AI technologies for data mining/analysis is preferred.

10+ yrs exp

Save