below marketmost similar roles pay hereabove market
This role pays less than
61%
of similar roles. Most pay
$169,625–$229,100
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The PHY Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless PHY and its interfaces within the wireless communication SoC. The role involves collaborating with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building block-level testbenches with reference models, executing directed and constrained random tests, and managing bug tracking. The candidate will utilize Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab, and shell, Python, and Perl scripting. The position requires expertise in ASIC verification flows, coverage models, and wireless protocols like Bluetooth, UWB, WLAN, or Zigbee. Additionally, the role involves using AI technologies for data mining and supporting validation via Palladium and FPGA.
Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem level test benches using reference models and best-in-class DV methodology.
Develop and execute directed and constrained random tests to identify and debug design failures.
Create and analyze coverage models to identify gaps and add necessary test cases.
Use machine learning and AI technologies to identify design issues and ensure verification quality.
Support PHY subsystem validation using Palladium and FPGA platforms.
Improve overall DV methodology and flows through collaboration with team members.
What we're looking for
Minimum requirement of a bachelor's degree.
MSEE with 2+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion (preferred).
Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage (preferred).
Experience of using Matlab/C reference model and bit-accurate verification (preferred).
Verification experience of wireless/wired communication block/subsystem (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficient in shell, Python, and Perl scripting (preferred).