PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $129,300–$225,300 / yr
Posted: 57 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $177k

$118k most similar roles pay here $237k

This role pays more than 53% of similar roles. Most pay $165,150–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · PHY Design Verification Engineer

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As a PHY Design Verification Engineer, you will join the wireless silicon development team to perform pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the communication SoC. You will collaborate with design and systems engineers to create verification plans from specifications, build reusable test benches using reference models, and execute both directed and constrained random tests. Your daily work involves managing bug tracking, analyzing coverage models, and utilizing machine learning and AI technologies for data mining and analysis. The role requires proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with experience in shell, Python, and Perl scripting. You will also support PHY subsystem validation using Palladium or FPGA hardware while ensuring high design quality across wireless protocols like Bluetooth, UWB, WLAN, or Zigbee.

Skills

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Matlab Machine Learning AI Bluetooth UWB WLAN Zigbee Constrained Random Testing

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem test benches using best-in-class DV methodologies.
Develop and execute directed and constrained random tests for the wireless PHY.
Debug failures, manage bug tracking, and work with designers to resolve issues.
Create and analyze coverage models while adding test cases to increase coverage.
Utilize machine learning and AI technologies to identify design and test bench issues.
Support PHY subsystem validation using Palladium or FPGA platforms.
Improve overall DV methodology and flow through collaboration with team members.

What we're looking for

A bachelor's degree is required.
An MSEE with 2+ years of verification experience for wireless/wired communication blocks or subsystems is preferred.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion is required.
Experience in ASIC verification flows including test bench development, constrained random testing, and coverage analysis is required.
Proficiency in shell, Python, and Perl scripting is required.
Experience using Matlab/C reference models and bit-accurate verification is preferred.
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee is preferred.
Experience with Palladium/FPGA validation and AI technologies for data mining/analysis is preferred.

10+ yrs exp

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