Packaging Substrate Engineer

As a Packaging Substrate Engineer within the Hardware Technology Packaging team, you will own and drive sophisticated package selection, new-generation structure development, and configuration optimization. You will be responsible for the design, technology, manufacturing, reliability, and roadmap of package substrates while collaborating with cross-functional teams to achieve optimal performance. Your daily work involves leading SoC package substrate technology pathfinding, defining roadmaps, and partnering with foundries and OSAT providers to move solutions from concept to high-volume manufacturing. You will solve technical issues throughout the product development cycle while managing material, chemistry, and mechanical engineering challenges. Key technical areas include Cu plating, lithography, dielectric materials, via formation, solder resist, and surface finish. You will also utilize Cadence Allegro platform tools for design review for manufacturing to address complex electronic packaging solutions for consumer electronics components.