As a SoC Architect at Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), you will join a team of experts designing proprietary coherent interconnects and memory controllers for Exynos SoCs, focusing on enabling advanced features like on-device machine learning. Your daily responsibilities include developing cache coherence protocols, NoC designs, and high-speed interface protocols to ensure seamless communication between IP blocks within complex semiconductor products. You will also collaborate with global teams to optimize system performance, power consumption, and area efficiency, using simulation tools and benchmarking techniques. The ideal candidate has extensive experience in SoC architecture, interconnect design, and proficiency in languages like C++, Python, Verilog/VHDL, alongside a deep understanding of cache subsystems and high-speed interface protocols such as PCIe and USB. Knowledge of memory subsystem design standards and the Android ecosystem is preferred, offering opportunities to work on cutting-edge technologies that power next-generation consumer devices.
Skills
C
C++
Python
Verilog
VHDL
AXI
ACE
CHI
PCIe
USB
Linux
Android
Arm Architecture
Cache Coherence Protocols
MESI
MOESI
Network-on-Chip
System-Level Design
Simulation Tools
Modeling
Benchmarking
What you'll do
Design and develop coherent interconnect architectures including cache coherence protocols.
Contribute to the specification, design, verification of interconnect IP blocks for SoCs.
Analyze and optimize interconnect performance, power consumption, and area efficiency.
Collaborate with global teams to ensure seamless integration of interconnect IP into SoC designs.
Take initiatives on moderate-to-complex projects to advance best practices in SoC architecture.
What we're looking for
15+ years of experience in SoC architecture or related fields with a Bachelor’s Degree.
Deep expertise in coherent interconnect architectures and cache subsystems design.
Proficient in high-speed interface protocols such as AXI, ACE, CHI, PCIe, and USB.
Strong understanding of system-level design principles and optimization techniques.
Skilled in programming languages including C/C++, Python, Verilog/VHDL.
Experience with Network-on-Chip (NoC) designs and cache coherence protocols.
Market check
Salary context
This
$180,200–$297,200
range sits above
80%
of similar postings on FindRole.
Peer median band
$162,050–$241,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$168,500–$235,750
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Samsung Electronics
Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.
Samsung Electronics currently has
33 open roles
on FindRole.
Listed pay typically runs
$172,500–$208,400
across 30 roles with salary data.