Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 38 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $216k

$132k most similar roles pay here $279k

This role pays more than 84% of similar roles. Most pay $167,450–$214,093 — the shaded band above. At the midpoint, this role pays about $216k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 985 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 971 roles with salary data.

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At a glance

TL;DR · Senior Design Engineer, Coherent High Speed Interconnect

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NVIDIA seeks a Senior Design Engineer to join its Coherent High Speed Interconnect team, focusing on the architecture and design of advanced high-speed interconnects like NVLINK-C2C for mobile SoCs and GPUs. This role involves collaborating with architects, software engineers, and circuit designers to create cutting-edge solutions that enable coherent integration between NVIDIA’s GPUs, DPUs, and CPUs via custom silicon chiplets. The ideal candidate will have a BS in Electrical Engineering or Computer Engineering and at least six years of relevant design experience, along with expertise in industry-standard interconnect protocols such as PCIe, CXL, AXI, and CHI. Proficiency in Verilog or System Verilog is essential, alongside knowledge of link layer stacks and physical layer aspects of memory and high-speed interfaces like SerDes. This position offers the chance to work on impactful projects spanning consumer graphics to AI and autonomous vehicles.

Skills

PCIe CXL AXI CHI Verilog SystemVerilog RTL design performance analysis power optimization Data link layer Physical layer Memory (DDR, LPDDR) SerDes Python CI/CD

What you'll do

Design state-of-the-art high-speed coherent interconnects for mobile SoCs and GPUs.
Collaborate with architects, software engineers, and circuit designers to deliver advanced interconnect solutions.
Enable the creation of integrated products using chiplets technology for NVIDIA’s GPUs, DPUs, and CPUs.
Utilize knowledge of industry-standard interconnect protocols like PCIE, CXL, AXI, CHI in design work.
Conduct performance analysis and power optimization for high-speed coherent interconnects.

What we're looking for

6+ years of relevant design experience in electrical engineering or computer engineering
Expertise in industry-standard interconnect protocols like PCIE, CXL, AXI, CHI
Understanding of link layer stacks including data link and physical layers
Experience with memory (DDR, LPDDR) and SerDes physical layers
Proficiency in architecture, RTL design, performance analysis, and power optimization
Strong knowledge of Verilog or System Verilog
Excellent communication skills and experience mentoring junior engineers

Senior PCB Designer, High-Speed Digital

Anduril Industries

Costa Mesa, CA 2 days ago $129,000–$194,000

Altium Cadence Allegro AutoCAD Electrical HyperLynx SIwave PIvision Python MATLAB HFSS ANSYS Sigrity Xilinx Vivado FPGA PCIe DDR SerDes EMI/EMC standards Differential pairs Controlled impedance routing Length matching Stackup design

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